Exar Corporation 48720 Kato Road, Fremont CA, 94538 510-668-7017 www.exar.com
SP3239E_100_020111
7
DESCRIPTION
The SP3239E device meets the EIA/TIA-232
and ITU-T V.28/V.24 communication protocols
and can be implemented in battery-powered,
portable, or hand-held applications such as
notebook or palmtop computers. The SP3239E
devices feature Exar's proprietary and patented
(U.S.-- 5,306,954) on-board charge pump cir-
cuitrythatgenerates±5.5VRS-232voltagelevels
from a single +3.0V to +5.5V power supply. The
SP3239E devices can guarantee a data rate of
250kbps fully loaded.
The SP3239E is a 5-driver/3-receiver device,
ideal for portable or hand-held applications.
The SP3239E includes one complementary
always-active receiver that can monitor an
external device (such as a modem) in shutdown.
This aids in protecting the UART or serial
controller IC by preventing forward biasing
of the protection diodes where V
CC may be
disconnected.
THEORY OF OPERATION
The SP3239E device is made up of three basic
circuit blocks:
1. Drivers
2. Receivers
3. The Exar proprietary charge pump
Drivers
The drivers are inverting level transmitters that
convert TTL or CMOS logic levels to 5.0V EIA/
TIA-232 levels with an inverted sense relative
to the input logic levels. Typically, the RS-232
output voltage swing is +5.4V with no load and
+5V minimum fully loaded. The driver outputs are
protected against infinite short-circuits to ground
without degradation in reliability. These drivers
comply with the EIA-TIA-232-F and all previous
RS-232 versions.
The drivers can guarantee a data rate of 250kbps
fully loaded with 3k in parallel with 1000pF,
ensuring compatibility with PC-to-PC communi-
cation software. All unused drivers inputs should
be connected to GND or V
CC.
The slew rate of the driver output is internally
limited to a maximum of 30V/s in order to meet
theEIAstandards(EIARS-232D2.1.7,Paragraph
5). The transition of the loaded output from HIGH
toLOWalsomeetsthemonotonicityrequirements
of the standard.
Figure 7 shows a loopback test circuit used to
test the RS-232 drivers. Figure 8 shows the test
results of the loopback circuit with all five drivers
active at 120kbps with typical RS-232 loads in
parallel with 1000pF capacitors. Figure 9 shows
the test results where one driver was active
at 250kbps and all five drivers loaded with an
RS-232 receiver in parallel with a 1000pF ca-
pacitor. A solid RS-232 data transmission rate
of 120kbps provides compatibility with many
designs in personal computer peripherals and
LAN applications.
Receivers
The receivers convert +5.0V EIA/TIA-232
levels to TTL or CMOS logic output levels. The
truthtablelogicoftheSP3239Edriverandreceiver
outputs can be found in Table 2.
Figure 6. Interface Circuitry Controlled by
Microprocessor Supervisory Circuit
SP3239E
28
25
3
1
27
4
26
GND
C1+
C1-
C2+
C2-
V+
V-
VCC
0.1F
+
C2
C5
C1
+
C3
C4
+
14
VCC
2
SHUTDOWN
P
Supervisor
IC
VCC
VIN
RESET
5k
24
23
22
16
21
20
18
5
6
7
8
9
11
RS-232
OUTPUTS
RS-232
INPUTS
T1IN
R1OUT
R1IN
T2OUT
R1OUT
T2IN
T3IN
T3OUT
T1OUT
R2IN
R3IN
R2OUT
R3OUT
UART
or
Serial C
TxD
RTS
DTR
RxD
CTS
DSR
DCD
RI
19
17
10
12
T4OUT
T4IN
T5IN
T5OUT
0.1F