參數(shù)資料
型號(hào): SP3249E
元件分類(lèi): RS-232
英文描述: 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
中文描述: 5V的高速RS - 232收發(fā)器與0.1uF電容
文件頁(yè)數(shù): 8/14頁(yè)
文件大?。?/td> 128K
代理商: SP3249E
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
8
Copyright 2002 Sipex Corporation
— V
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
produces –V
in the negative
terminal of C
, which is applied to the negative
side of capacitor C
. Since C
voltage potential across C
2
is 2 times V
CC
.
+
is at V
CC
, the
Phase 4
(Figure 15)
— V
transfer — The fourth phase of the clock
connects the negative terminal of C
to GND,
and transfers this positive generated voltage
across C
to C
, the V
storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C
, the
positive side of capacitor C
is switched to V
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
Since both V
+
and V
are separately generated
from V
, in a no–load condition V
+
and V
will
be symmetrical. Older charge pump approaches
that generate V
from V
+
will show a decrease in
the magnitude of V
compared to V
+
due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 500kHz. The external capacitors can
be as low as 0.1
μ
F with a 16V breakdown
voltage rating.
Figure 11. Charge Pump — Phase 2
V
CC
= +5V
10V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
+
+
V
CC
= +5V
5V
5V
+5V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
+
+
Figure 10. Charge Pump — Phase 1
Figure 12. Charge Pump Waveforms
Ch1 2.00V
Ch2
2.00V M 1.00
μ
s Ch1 1.96V
2
1
T
T
[
]
T
2
+6V
a) C
2+
b) C
2
-
-6V
0V
0V
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