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參數資料
| 型號： | SP3282EBEA |
| 元件分類： | RS-232 |
| 英文描述： | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| 中文描述： | 5V的高速RS - 232收發(fā)器與0.1uF電容 |
| 文件頁數： | 8/15頁 |
| 文件大小： | 307K |
| 代理商： | SP3282EBEA |
Date: 02/24/05
SP3282EB Intelligent +2.35V to +5.5V RS-232 Transceivers
Copyright 2005 Sipex Corporation
8
— V
charge storage — During this phase of the
clock cycle, the positive side of capacitors C
and
C
are initially charged to V
CC
. C
to GND and the charge in C
1
. Since C
tial across capacitor C
2
is now 2 times V
CC
.
+
is then switched
–
is transferred to C
2
–
+
is connected to V
, the voltage poten-
Phase 2 (Figure 12)
— V
transfer — Phase two of the clock
connects the negative terminal of C
to the V
storage capacitor and the positive terminal of C
to
GND. This transfers a negative generated voltage
to
C
.
This
generated
regulated to a minimum voltage of -5.5V (V
CC
>
3.3V) and -4.0V (V
< 3.1V).
Simultaneous with the transfer of the voltage to C
3
,
the positive side of capacitor C
is switched to V
CC
and the negative side is connected to GND.
voltage
is
Phase 3 (Figure 13)
— V
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
produces –V
in the negative
terminal of C
1
, which is applied to the negative side
of capacitor C
. Since C
potential across C
2
is 2 times V
CC
.
+
is at V
CC
, the voltage
Phase 4 (Figure 14)
— V
transfer — The fourth phase of the clock
connects the negative terminal of C
to GND, and
transfers this positive generated voltage across C
2
to C
, the V
storage capacitor. This voltage is
regulated to +5.5V (V
> 3.3V) and +4.0V
(V
<3.1V). At this voltage, the internal oscillator
is disabled. Simultaneous with the transfer of the
voltage to C
4
, the positive side of capacitor C
is
switched to V
and the negative side is connected
to GND, allowing the charge pump cycle to begin
again. The charge pump cycle will continue as
long as the operational conditions for theinternal
oscillator are present.
Since both V
+
and V
–
are separately generated
Charge Pump Capacitor Selection
The charge pump capacitors C1-C4 and bypass
C5 can be of any type including ceramic. If
polarized capacitors are used, refer to figure 3
application diagram for proper orientation. The
following chart illustrates the minimum capaci-
tor valve for a given input voltage range.
from V
, in a no–load condition V
+
and V
–
will be
symmetrical. Older charge pump approaches that
generate V
–
from V
+
will show a decrease in the
magnitude of V
–
compared to V
+
due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 500kHz. The external capacitors should
be 0.22
μ
F with a 16V working voltage rating for
a V
CC
input range of +2.35V to +5.5V.
Figure 11. Charge Pump — Phase 1
V
CC
V
DD
Storage Capacitor
V
SS
Storage Capacitor
C
1
C
2
+
-
-
+
C
4
C
3
+
-
+
-
-V
CC
-V
CC
+V
CC
V
CC
(V)
3.0 to 3.6
4.5 to 5.5
2.35 to 5.5
C1 and C5 (
μ
F)
0.1
0.047
0.22
C2,C3,C4 (
μ
F)
0.1
0.33
0.22
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SP3282EBEA/TR | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Intelligent +2.35V to +5.5V RS-232 Transceivers |
| SP3282EBEY | 制造商:Exar Corporation 功能描述: 制造商:SIPEX 功能描述: |
| SP3282EBEY/TR | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Intelligent +2.35V to +5.5V RS-232 Transceivers |
| SP3282EBEY-L | 制造商:Exar Corporation 功能描述:TRANSCEIVER RS-232 +1.8V TO +5.5V |
| SP32R0FL | 制造商:TE Connectivity 功能描述:SP3 2R0 1% LOOSEFixed Resistor |
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