參數(shù)資料
型號(hào): SP3282EBEY
元件分類: RS-232
英文描述: 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
中文描述: 5V的高速RS - 232收發(fā)器與0.1uF電容
文件頁(yè)數(shù): 7/15頁(yè)
文件大小: 307K
代理商: SP3282EBEY
7
Date: 02/24/05
SP3282EB Intelligent +2.35V to +5.5V RS-232 Transceivers
Copyright 2005 Sipex Corporation
Since receiver input is usually from a transmission
line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, an internal 5k
pulldown resistor to
ground will commit the output of the receiver to a
HIGH state.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. #5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump uses a four–phase voltage
shifting technique to attain symmetrical
±
5.5V
power supplies. The internal power supply con-
sists of a regulated dual charge pump that provides
output voltages
±
5.5V regardless of the input
voltage (V
) over the +3.3V to +5.5V range.
This is important to maintain compliant RS-232
levels
regardless
fluctuations. The charge pump will provide out-
put voltage levels of
±
4.0V when the input voltage
(V
) is from +3.1V to +2.35V.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V ( V
> 3.3V ) and 4.0V (V
< 3.1V), the charge pump
is enabled. If the output voltages exceed a
magnitude of 5.5V (V
> 3.3V) and 4.0V (V
<
3.1V), the charge pump is disabled. This oscilla-
tor controls the four phases of the voltage shifting
(Figure 10).
A description of each phase follows.
Phase 1 (Figure 11)
of
power
supply
Figure 6. Loopback Test Circuit for RS-232 Driver Data
Transmission Rates
Figure 10. Charge Pump Waveforms
Ch1 2.00V
Ch2
2.00V M 1.00
μ
s Ch1 1.96V
2
1
T
T
[
]
T
2
+6V
a) C
2+
b) C
2
-
-6V
0V
0V
Figure 7. Loopback Test Circuit Result at 120kbps
(All Drivers Fully Loaded)
Figure 8. Loopback Test Circuit result at 250kbps
(All Drivers Fully Loaded)
SP3282EB
TxIN
TxOUT
C1+
C1-
C2+
C2-
V+
V-
V
CC
0.1
μ
F
0.1
μ
F
0.1
μ
F
+
C2
C5
C1
+
+
C3
C4
+
+
0.1
μ
F
0.1
μ
F
ILOGIC
V
CC
5k
RxIN
RxOUT
OULOGIC
SHUTDOWN
GND
V
CC
ONLINE
1000pF
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