參數資料
型號: SP3489CT
英文描述: +3.3V Low Power Quad RS-485/RS-422 Line Receivers
中文描述: 3.3V低功耗四RS-485/RS-422收發(fā)線接收器
文件頁數: 3/9頁
文件大?。?/td> 116K
代理商: SP3489CT
3
10/16/02 SP3488/3489 Low Power Quad RS-485/422 Line Receivers
Copyright 2002 Sipex Corporation
A
B
54
15pF
DI
1/4 SP3486
1/4 SP3488
15pF EN
EN
ROn
DRIVER
RCVR
C
L
Figure 1. Timing Test Circuit
S
1
RCVR
S
2
V
CC
1k
C
L
1k
Figure 2. Enable/Disable Timing Test Circuit
Pin 6 — RI
2
A — Receiver 2 input A.
Pin 7 — RI
2
B — Receiver 2 input B.
Pin 8 — GND — Digital Ground.
Pin 9 — RI
3
B — Receiver 3 input B.
Pin 10 — RI
3
A
Receiver 3 input A.
Pin 11 — RO
— Receiver 3 Output — If
Receiver 3 output is enabled, if RI
A > RI
B by
200mV, Receiver 3 output is high. If Receiver 3
output is enabled, and if RI
A < RI
3
B by
200mV, Receiver 3 output is low.
Pin 12 — EN — Receiver Output Enable. Please
refer to SP3488 Truth Table (1).
SP3488 PINOUT
Pin 1 — RI
1
B — Receiver 1 input B.
Pin 2 — RI
1
A
Receiver 1 input A.
Pin 3 — RO
— Receiver 1 Output — If Re-
ceiver 1 output is enabled, if RI
A
> RI
B by
200mV, Receiver output is high. If Receiver 1
output is enabled, and if RI
1
A
< RI
1
B
by 200mV,
Receiver 1 output is low.
Pin 4 — EN — Receiver Output Enable. Please
refer to SP3488
Truth Table (1)
.
Pin 5 — RO
— Receiver 2 Output — If Re-
ceiver 2 output is enabled, if RI
A > RI
B by
200mV, Receiver 2 output is high. If Receiver 2
output is enabled, and if RI
A < RI
2
B by
200mV, Receiver 2 output is low.
SP3488
RI
1
B
RI
1
A
RO
1
EN
RO
2
RI
2
A
RI
2
B
GND
V
CC
RI
4
B
RI
4
A
RO
4
EN
RO
3
RI
3
A
RI
3
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
4
3
2
SP3489
RI
1
B
RI
1
A
RO
1
EN
1
/EN
2
RO
2
RI
2
A
RI
2
B
GND
V
CC
RI
4
B
RI
4
A
RO
4
EN
3
/EN
4
RO
3
RI
3
A
RI
3
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
4
3
2
PINOUT
相關PDF資料
PDF描述
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SP3488EP +3.3V Low Power Quad RS-485/RS-422 Line Receivers
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