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參數(shù)資料
| 型號(hào)： | SP432CN |
| 英文描述： | High Speed, Low Power Quad RS-422 Differential Line Receiver |
| 中文描述： | 高速，低功耗四的RS - 422差分線路接收器 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 363K |
| 代理商： | SP432CN |
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SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver Copyright 1997 Sipex Corporation
DESCRIPTION
The
SP432
is a low-power quad differential line
receiver designed for digital data transmission
meeting Federal Standards 1020 and 1030 as
well as the specifications of the EIA standard
RS-422 protocol. The
SP432
features Sipex's
BiCMOS process allowing low power opera-
tional characteristics of CMOS technology
while meeting all of the demands of the RS-422
serial protocol to at least 50Mbps under load in
harsh environments.
The RS-422 standard is ideal for multi-drop
applications and for long-distance communica-
tion. The RS-422 protocol allows up to 10
drivers to be connected to a data bus, making it
an ideal choice for multi-drop applications. Since
the cabling can be as long as 4,000 feet, the
RS-422 receivers have an input sensitivity of
200mV over the wide (-7.0V to +7.0V) common
mode range to accommodate ground potential
differences. Internal pull-up and pull-down
resistors prevent output oscillation on unused
channels. Because the RS-422 is a differential
interface, data is virtually immune to noise in the
transmission line.
Figure 6. Two-Wire Balanced Systems, RS-422
*R
T
ENABLE
DATA
DATA
OUTPUT
*R
is optional although highly
recommended to reduce reflection.
Figure 5. Truth Table, Enable/Disable Function
Common to all Four RS-422 Receivers
The
SP432
accepts RS-422 levels and translates
these into TTL or CMOS input levels. The
SP432
features active HIGH and active LOW receiver
enable controls common to all four receiver
channels. A logic HIGH on the ENABLE pin
(pin 4) or a logic LOW on the ENABLE pin (pin
12) will enable the differential receiver outputs.
A logic LOW on the ENABLE pin (pin 4) or a
logic HIGH on the ENABLE pin (pin 12) will
tri-state the receiver outputs.
The RS-422 line receivers feature high source
and sink current capability. All receivers are
internally protected against short circuits on their
inputs. The receivers feature tri-state
outputs with 6mA source and sink capability.
The typical receiver propagation delay is 8ns
(30ns max).
To minimize reflections, the multipoint bus
transmission line should be terminated at both
ends in its characteristic impedance, and stub
lengths off the main line should be kept as short
as possible.
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相關(guān)代理商/技術(shù)參數(shù) |
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