14
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
Copyright 2004 Sipex Corporation
Figure 17. Charge Pump Waveforms
Figure 14a. Charge Pump Phase 2 for
±
10V.
Figure 15. Charge Pump Phase 3.
V
CC
= +5V
–10V
V
DD
Storage Capacitor
C
1
C
2
C
4
+
+
+
–
–
–
V
SS
Storage Capacitor
C
3
+
–
V
CC
= +5V
–5V
–5V
+5V
V
DD
Storage Capacitor
C
1
C
2
C
4
+
+
+
–
–
–
V
SS
Storage Capacitor
C
3
+
–
Figure 16. Charge Pump Phase 4.
Figure 14b. Charge Pump Phase 2 for
±
5V.
V
CC
= +5V
V
DD
Storage Capacitor
C
1
C
2
C
4
+
+
+
–
–
–
V
SS
Storage Capacitor
C
3
+
–
–5V
V
CC
= +5V
+10V
V
DD
Storage Capacitor
C
1
C
2
C
4
+
+
+
–
–
–
V
SS
Storage Capacitor
C
3
+
–
GND
–10V
+10V
C
2
+
C
2
–
(a)
(b)
GND
C
+
+5V
GND
C
2
–5V
GND
–
Phase 2 (
±
10V)
— V
transfer — Phase two of the clock con-
nects the negative terminal of C
to the V
SS
storage capacitor and the positive terminal of C
2
to ground, and transfers the generated –l0V or
the generated –5V to C
. Simultaneously, the
positive side of capacitor C
is switched to +5V
and the negative side is connected to ground.
Phase 2 (
±
5V)
— V
& V
DD
charge storage — C
nected to V
to recharge the C
capacitor. C
2
is switched to ground and C
The 5V charge from Phase 1 is now transferred
+
is recon-
+
–
is connected to C
3
.
to the V
storage capacitor. V
SS
receives a
continuous charge from either C
. With
the C1 capacitor charged to 5V, the cycle begins
again.
Phase 3
— V
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
produces –5V in the negative
terminal of C
, which is applied to the negative
side of capacitor C
. Since C
voltage potential across C
is l0V. For the 5V
output, C
potential on C
2
is only +5V.
+
is at +5V, the
+
is connected to ground so that the