參數(shù)資料
型號(hào): SP5055
廠商: Mitel Networks Corporation
英文描述: 2.6GHz Bidirectional I2C BUS Controlled Synthesiser
中文描述: 2.6GHz的雙向I2C總線控制合成器
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 197K
代理商: SP5055
4
SP5055
A0
0
1
0
1
0
Voltage input to P6
0.6V
CC
to 13.2V
0·45V
CC
to 0·6V
CC
0·3V
CC
to 0·45V
CC
0·15V
CC
to 0·3V
CC
0 to 0.15V
CC
Table 3 ADC levels
Bits 3, 4 and 5 (I2,I1,I0) show the status of the I/O Ports P7,
P5 and P4 respectively. A logic 0 indicates a low level and a logic
1 a high level. If the ports are to be used as inputs they should
be programmed to a high impedance state (logic 1). These
inputs will then respond to data complying with TTL type voltage
levels. Bits 6, 7 and 8 (A2,A1,A0) combine to give the output of
the 5 level ADC.
The 5 level ADC can be used to feed AFC information to
the microprocessor from the IF section of the receiver, as
illustrated in the typical application circuit.
APPLICATION
A typical Application is shown in Fig. 4. All input/output
interface circuits are shown in Fig. 6.
Table 1 Write data format (MSB transmitted first)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits
1
2
14
2
6
CP
P6
0
2
13
2
5
T1
P5
0
2
12
2
4
T0
P4
0
2
11
2
3
1
P3
MA0
2
9
2
1
1
X
MA1
2
10
2
2
1
X
A
A
A
A
A
MSB
1
0
2
7
1
P7
LSB
0
2
8
2
0
OS
P0
Table 2 Read data format (MSB is transmitted first)
Byte 1
Byte 2
Address
Status byte
1
FL
0
I2
0
I1
0
I0
MA0
A1
MA1
A2
A
A
1
POR
1
A0
A
MA1, MA0
CP
T1
T0
OS
P7, P6, P5, P4,
P3, P0
POR
FL
I2, I1, I0
A2, A1, A0
X
:
:
:
:
:
:
:
Acknowledge bit
Variable address bits (see Table 4)
Charge Pump current select
Test mode selection
Charge pump disable
Varactor drive Output disable Switch
Control output states
:
:
:
:
:
Power On Reset indicator
Phase lock detect flag
Digital information from Ports P7, P5 and P4, respectively
5 Level ADC data from P6 (see Table 3)
Don't care
Table 4 Address selection
MA0
0
1
0
1
MA1
0
0
1
1
Voltage input to P3
0V to 0·2V
CC
Always valid
0·3V
CC
to 0·7V
CC
0·8V
CC
-13.2V
A1
0
1
1
0
0
A2
1
0
0
0
0
Fig. 3 Data formats
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