參數(shù)資料
型號(hào)： SP508
英文描述： Rugged 40Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors(40Mbps差分傳輸速率，8通道多協(xié)議收發(fā)器（帶可編程DCE/DTE和終端電阻器）)
中文描述： 堅(jiān)固40Mbps的，8通道多協(xié)議收發(fā)器，具有可編程DCE的/ DTE和終端電阻（40Mbps的差分傳輸速率，8通道多協(xié)議收發(fā)器（帶可編程DCE的/ DTE的和終端電阻器））
文件頁(yè)數(shù)： 22/27頁(yè)
文件大?。?/td> 246K
代理商： SP508
22
rev. 8/31/00
SP508 Enhanced WAN Multi–Mode Serial Transceiver
Copyright 2000 Sipex Corporation
P
The same receivers also incorporate a termination
network internally for V.35 applications. For
V.35, the receiver input termination is a “Y”
termination consisting of two 51
resistors
connected in series and a 124
resistor connected
between the two 50
resistors and V35RGND
output. The V35RGND is usually grounded. The
receiver itself is identical to the V.11 receiver.
The differential receivers can be configured to
be ITU-T-V.10 single-ended receivers by
internally connecting the non-inverting input to
ground. This is internally done by default from
the decoder. The non-inverting input is rerouted
to V10GND and can be grounded separately.
The ITU-T-V.10 receivers can operate over
1Mbps and are used in RS-449/V.36, E1A-530,
E1A-530A and X.21 modes as Category II signals
as indicated by their corresponding specifications.
All receivers include an enable/disable line for
disabling the receiver output allowing convenient
half-duplex configurations. The enable pins will
either enable or disable the output of the receivers
according to the appropriate active logic
illustrated on
Figure 45
. The receiver’s enable
lines include an internal pull-up or pull-down
device, depending on the active polarity of the
receiver, that enables the receiver upon power up
if the enable lines are left floating. During disabled
conditions, the receiver outputs will be at a high
impedance state. If the receiver is disabled any
associated termination is also disconnected from
the inputs.
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open, terminated but open, or shorted together.
For single-ended V.28 and V.10 receivers, there
are internal 5k
pull-down resistors on the inputs
which produces a logic high (“1”) at the receiver
outputs. The differential receivers have a
proprietary circuit that detect open or shorted
inputs and if so, will produce a logic HIGH (“1”)
at the receiver output.
CHARGE PUMP
The charge pump is a
Sipex
-patented design
(5,306,954) and uses a unique approach compared
to older less-efficient designs. The charge pump
still requires four external capacitors, but uses
four-phase voltage shifting technique to attain
symmetrical power supplies. The charge pump
V
and V
outputs are regulated to +5.8V and
-5.8V, respectively. There is a free-running
oscillator that controls the four phases of the
voltage shifting. A description of each phase
follows.
Phase 1
__V
charge storage ——During this phase of
the clock cycle, the positive side of capacitors C
1
and C
are initially charged to V
. C+ is then
switched to ground and the charge in C
- is
transferred to C
-. Since C
+ is connected to V
,
the voltage potential across capacitor C
2
is now
2
X
V
CC
.
Phase 2
—V
transfer —Phase two of the clock connects
the negative terminal of C
to the V
storage
capacitor and the positive terminal of C
to
ground, and transfers the negative generated
voltage to C
. This generated voltage is regulated
to –5.8V. Simultaneously, the positive side of
the capacitor C
is switched to V
CC
and the
negative side is connected to ground.
Phase 3
—V
charge storage —The third phase of the
clock is identical to the first phase—the charge
transferred in C
produces –V
in the negative
terminal of C
which is applied to the negative
side of the capacitor C
. Since C
2
+ is at V
CC
, the
voltage potential across C
2
is 2
X
V
CC
.
Phase 4
—V
transfer —The fourth phase of the clock
connects the negative terminal of C
to ground,
and transfers the generated 5.8V across C
to C
4
,
the V
storage capacitor. This voltage is
regulated to +5.8V. At the regulated voltage, the
internal oscillator is disabled and simultaneously
with this, the positive side of capacitor C
is
switched to V
and the negative side is connected
to ground, and the cycle begins again. The charge
pump cycle will continue as long as the
operational conditions for the internal oscillator
are present.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SP508/1.2/BLACK 制造商:Farnell / Pro-Power 功能描述:HEATSHRINK 50.8MM BLACK 1.2M 制造商:pro-power 功能描述:HEATSHRINK, 50.8MM, BLACK, 1.2M 制造商:pro-power 功能描述:HEAT SHRINK TUBING, 50.8MM ID, PO, BLK, 3.94FT; I.D. Supplied - Metric:50.8mm; I.D. Supplied - Imperial:2"; I.D. Recovered Max - Metric:25.4mm; I.D. Recovered Max - Imperial:1"; Shrink Ratio:2:1; Shrink Tubing / Boot Color:Black ;RoHS Compliant: Yes
SP508/1.2/BLACK 制造商:Farnell / Pro-Power 功能描述:HEAT SHRINK 50.8MM BLACK 1.2M
SP508/1.2/BLUE 制造商:Farnell / Pro-Power 功能描述:HEAT SHRINK 50.8MM BLUE 1.2M
SP508/1.2/BLUE 制造商:Farnell / Pro-Power 功能描述:HEAT SHRINK 50.8MM BLUE 1.2M
SP508/1.2/CLEAR 制造商:Farnell / Pro-Power 功能描述:HEAT SHRINK 50.8MM CLEAR 1.2M
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