14
Date: 10/02/04
SP6122 Low Voltage, Micro 8, PFET, Buck Controller Copyright 2004 Sipex Corporation
P
SH(MAX)
1/2 I
OUT(MAX)
V
IN(MAX)
(t
RISE +
t
FALL
)F
S
where t
RISE
(SP6122) for 8A PMOS is typi-
cally 20ns and t
FALL
(SP6122) for 8A PMOS
is typically 40ns.
Switching losses need to be taken into
account for high switching frequency, since
they are directly proportional to switching
frequency. The conduction losses associ-
ated with the PMOS is determined by:
P
CH(MAX)
= I
OUT (MAX)2
R
DS(ON)
D
Where R
DS(ON)
= drain to source on resis-
tance.
The total power losses of the PMOS are the
sum of switching and conduction losses.
For input voltages of 3.3V and 5V, conduc-
tion losses often dominate switching losses.
Therefore, lowering the R
DS(ON)
of the PMOS
always improves efficiency even though it
gives rise to higher switching losses due to
increased C
RSS
.
For the SP6122 design example, the
Fairchild PMOS PDS6375 was selected for
its low R
DS(ON)
and good switching charac-
teristics including low gate charge at the
3.3V input. Using table 1 values for R
DS(ON)
and t
RISE
and t
FALL
for the SP6122, we
calculate;
P
SH(MAX)
= 119mW and P
CH(MAX)
= 203mW.
R
DS(ON)
varies greatly with the gate driver
voltage. The MOSFET vendors often specify
R
DS(ON)
on multiple gate to source voltages
(V
GS
), as well as provide typical curve of
R
DS(ON)
versus V
GS
. For 5V input, use the
R
DS(ON)
specified at 4.5V V
GS
. At the time of
this publication, vendors, such as Fairchild,
Siliconix and International Rectifier, have
started to specify R
DS(ON)
at V
GS
less than
3V. This has provided necessary data for
designs in which these MOSFETs are driven
with 3.3V and made it possible to use
SP6122 in 3.3V only applications.
Thermal calculation must be conducted to
ensure the MOSFET can handle the maxi-
mum load current. The junction tempera-
ture of the MOSFET, determined as follows,
must stay below the maximum rating.
T
J(MAX)
= T
A (MAX)
+ P
MOSFET(MAX)
R
θ
JA
where
T
A (MAX)
= maximum ambient temperature
P
MOSFET(MAX)
= maximum power dissipation
of the MOSFET, including both switching
and conduction losses
R
θ
JA
= junction to ambient thermal resistance.
R
θ
JA
of the device depends greatly on the
board layout, as well as device package.
Significant thermal improvement can be
achieved in the maximum power dissipation
through the proper design of copper mount-
ing pads on the circuit board. For example,
in a SO-8 package, placing two 0.04 square
inches copper pad directly under the pack-
age, without occupying additional board
space, can increase the maximum power
from approximately 1 to 1.2W.
For the PMOS PDS6375, assuming T
A (MAX)
= 20
°
C, P
MOSFET(MAX)
= P
SH(MAX)
+ P
CH(MAX)
= 321mW, and assuming per PDS6375
data sheet, R
θ
JA
= 50
°
C/W if using 0.5 in
2
pad of 2oz Cu,
T
J(MAX)
= 36
°
C
which is only a 16
°
C rise from ambient.
SCHOTTKY DIODE SELECTION
The schottky diode is selected for low for-
ward voltage, current capability and fast
switching speed. The average power dissi-
pation of the schottky diode is determined
by
P
DIODE
= V
F
I
OUT
(1-
D)
Where V
F
is the forward voltage of the
Schottky diode at I
OUT
.
Guidelines for Component Selection:
continued