6
Date: 5/25/04
SP6231 500mA, 3.3V Linear Regulator
Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS: continued
Figure 9. Supply Switching under full load, Vaux=3.3V.
Ch 1=Vin; Ch 2=Vout; Ch 3=Iload (500mA/div).
Figure 8. Load transients. 1 - V
OUT
, 4 - I
LOAD
(500mA/div)
Input Capacitor
A small capacitor 2.2
μ
F or higher, is required
from V
IN
to GND and V
AUX
to GND to create a
high frequency bypass for the LDO amplifier.
Any ceramic or tantalum capacitor may be used
at the inputs. Capacitor ESR (equivalent series
resistance) should be smaller than 1
.
Output Capacitor
An output capacitor is required between V
OUT
and GND to prevent oscillations. A 2.2
μ
F ca-
pacitor ensures unconditional stability from no
load to full load over the entire input voltage and
temperature range. Larger capacitor values im-
prove the regulator’s transient response. The
output capacitor value may be increased with-
out limit. The output capacitor should have an
ESR below 3
and a resonant frequency above
1MHz.
Thermal Considerations
The SP6231 is designed to provide 500mA of
continuous current. Maximum power dissipa-
tion can be calculated based on the output cur-
rent and voltage drop across the device. To
determine the maximum power dissipation in
the package, use the junction-to-ambient ther-
mal resistance of the device and the following
basic equation:
P
D(max)
= (T
J(max)
- T
A
) /
θ
JA
T
J(max)
is the maximum junction temperature of
the die and is 125
°
C. T
A
is the ambient operating
temperature.
θ
JA
is the junction-to-ambient ther-
mal resistance for the regulator and is layout and
package dependent.
The actual power dissipation of the regulator
circuit can be determined using one simple
equation:
PD = (V
IN
- V
OUT
) * I
OUT
+ V
IN
* I
GND
(V
IN
- V
OUT
) * I
OUT
Substituting P
D(max)
for P
D
and solving for the
operating conditions that are critical to the ap-
plication gives the maximum operating condi-
tions for the regulator circuit. For example if we
are operating the SP6231 at room temperature,
with a minimum footprint layout, we can deter-
mine the maximum input voltage for a set output
current.
P
D(max)
= (125
°
C - 25
°
C) / 57
°
C/W = 1754mW
(
θ
JA
= 57
°
C/W for the 3x3 MLP package)
Notice that the LDO in the MLP package has a
much smaller
θ
JA
than in comparable dimen-
sions. For comparison,
θ
JA
= 220
°
C/W for a
SOT-23 package.
APPLICATION INFORMATION