- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄202097 > SP674AT/B (ANALOG DEVICES INC) 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 PDF資料下載
參數(shù)資料
| 型號(hào)： | SP674AT/B |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁(yè)數(shù)： | 2/22頁(yè) |
| 文件大?。?/td> | 294K |
| 代理商： | SP674AT/B |
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)
STANDARDIZED
MICROCIRCUIT DRAWING
DEFENSE ELECTRONICS SUPPLY CENTER
DAYTON, OHIO 45444
SIZE
A
5962-91690
REVISION LEVEL
B
SHEET
8
DESC FORM 193A
JUL 94
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/
-55°C
T +125°C
A
V
= +15 V, V
= +5 V,
CC
LOGIC
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
STS delay from CE
10/
tDSC
See figure 5
1, 2, 3
01,02
200
ns
03
225
CE pulse width
9/tHEC
All
50
C
S
to CE setup
tSSC
50
Conversion time
13/
tC
8-bit cycle, see figure 5
9, 10, 11
All
6
10
s
12-bit cycle, see figure 5
9
15
C
S
low during CE
tHSC
See figure 5
9, 10, 11
All
50
R/C
to CE setup
tSRC
50
R/C
low during CE
high
tHRC
50
A to CE setup
0
tSAC
0
A valid during CE
0
high
tHAC
50
Access time (from CE)
12/
tDD
See figure 6
9, 10, 11
All
150
ns
Data valid after CE
low
11/
tHD
01,02
04
25
11
03
15
9, 10
25
Output float delay
11/tHL
9, 10, 11
All
150
C
S
to CE setup
tSSR
All
50
R/C
to CE setup
tSRR
All
0
Sample and hold 14/
acquisition time
tacq
T = +25°C
A
9
01,02
04
1.2
2.0
s
A to CE setup
0
tSAR
See figure 6
9, 10, 11
All
50
ns
See footnotes at end of table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TB100-25L5QC16 | 20 A, BARRIER STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| TB100-25L6QC10 | 20 A, BARRIER STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| TB100-06L5QC10 | 20 A, BARRIER STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| TB100-06L6QC13 | 20 A, BARRIER STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| TB100-06L6QC7 | 20 A, BARRIER STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP674AU | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:12-Bit Sampling A/D Converters |
| SP674AU/B | 制造商: 功能描述:Analog Digital Converter, Single, 12 Bit, 28 Pin, DIP |
| SP674AU883 | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:12-bit Sampling A/D Converters |
| SP674BA | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:12-Bit Sampling A/D Converters |
| SP674BB | 制造商:SIPEX 制造商全稱(chēng):Sipex Corporation 功能描述:12-Bit Sampling A/D Converters |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。