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參數(shù)資料
| 型號： | SP674BJL |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大小： | 150K |
| 代理商： | SP674BJL |
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
Copyright 2000 Sipex Corporation
11
CE
CS
R/C
A0
STS
DB11–
DB0
HIGH IMPEDANCE
tDSC
tC
tHAC
tSAC
tHRC
tHEC
tSRC
tSSC
CONVERT MODE TIMING
CHARACTERISTICS
Typical @ 25C, V
CC = +15V or +10V, VLOGIC
= +5V, V
EE = 0V, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
tDSC STS Delay from CE
200
ns
tHEC CE Pulse Width
50
ns
tSSC CS to CE Setup
50
ns
tHSC CS Low during CE High
50
ns
tSRC R/C to CE Setup
50
ns
tHRC R/C Low during CE High
50
ns
tSAC A0 to CE Setup
0
ns
tHAC A0 Valid during CE High
50
ns
tC
Conversion Time1, 3, 4
See specifications
NOTES:
1.
Parameters guaranteed by design and sample tested.
2.
Parameters 100% tested @ 25C on special orders.
3.
100% tested.
4.
T
MIN to TMAX.
Figure 6. Convert Mode Timing
OBSOLETE
-
HIST
ORICAL
REFERENCE
ONL
Y
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