SP691AEB/03
SP691A/693A Evaluation Board Manual
2
Copyright 2000 Sipex Corporation
BOARD LAYOUT
The
SP691A/693A Evaluation Board
has been
designed to easily and conveniently provide
access to all pins of the SP691A/693A device
under test. Position the board with the silkscreen
lettering upright (also see drawing on the front
page of this manual) and you will see two
vertical rows of eight pins each, which represent
the 16 pins of the SP691A/693A device starting
in the top left with V
as pin one. The pin
receptacles are raised female pins which can
accommodate easy-hook connection leads for
power and meter connections, as well as scope
probe hooks and grounds for waveform
measurements.
The 16 pin SP691A/693A may be installed in
one of 3 locations: U1 for DIP or DIP sockets,
U3 for SOICs or U2 for SOIC sockets. The five
input pins for the SP691A/693A are provided
with extra Input Probe Points for connecting
inputs to these pins. For example pin 11 WDI
has nearby pins V
and GND to connect to for
evaluation of WDI timeout. These female
receptacle pins can be jumpered together with
easy-hook connectors or stripped back solid wire
leads. In the case of inputs OSC IN, OSC SEL
or PFI, a resistor or capacitor with leads may be
pushed into the female receptacle pins to make
easy connections. Also, mating male pins (see
List of Materials) may be soldered to the
components and inserted into the receptacle pins.
USING THE EVALUATION BOARD
Connect the
SP691A/693A Evaluation Board
to the power supplies for V
and V
(see the section Power Supply Connections
following the table SP691A/693A Pin
Assignments). It is good practice to not switch
power on until power connections are made to
the evaluation board.
Evaluating Pin Functions
Pin 1 – V
– Backup-Battery Input.
Connect to external supply, battery or capacitor
and charging circuit. If this pin is not used,
connect to GND.
Pin 2 – V
– Output Supply Voltage. This
function is used to provide power supply
switching of either V
or V
to an
external device like a CMOS RAM to ensure a
constant supply for the memory. To evaluate this
function, vary the V
voltage for a set V
voltage until you simulate the following
conditions: V
OUT
connects to V
when V
is
greater than V
and V
is above the reset
threshold. When V
falls below V
and V
is below the reset threshold, V
connects to
V
. Start with V
voltage of about 2.8 to
4.0V and vary V
from 0V to 5V to 0V and
observe V
. (Note: a 0.1
μ
F bypass
capacitor (C1) is connected from V
to GND).
Connect V
OUT
to V
CC
if no backup battery is used.
Pin 3 – V
– Input Supply Voltage - +5V input.
A 0.1(F bypass capacitor (C2) is connected
from V
CC
to GND.
Pin 4 – GND – Ground reference for all signals.
Pin 5 – BATT ON – Battery On Output. Goes
high when V
OUT
switches to V
BATT
. Goes
low when V
switches to V
the base of a PNP through a current-limiting
resistor to BATT ON for V
OUT
current
requirements greater than 250mA.
Pin 6 - LOWLINE - LOWLINE Output goes
low when V
falls below the reset threshold.
It returns high as soon as V
rises above the
reset threshold. The output can be used to
generate a NMI (non-maskable interrupt) if the
unregulated supply is inaccessible.