參數(shù)資料
型號(hào): SP706EU
英文描述: Low Power Microprocessor Supervisory Circuits
中文描述: 低功耗微處理器監(jiān)控電路
文件頁(yè)數(shù): 10/18頁(yè)
文件大小: 197K
代理商: SP706EU
SP705DS/09
SP705 Low Power Microprocessor Supervisory Circuits
Copyright 2000 Sipex Corporation
10
Typically, WDO will be connected to the
non-maskable interrupt input (NMI) of a
μ
P.
When V
CC
drops below the reset threshold,
WDO will go LOW whether or not the watch-
dog timer has timed out. Normally this would
trigger an NMI but RESET goes LOW simulta-
neously, and thus overrides the NMI.
If WDI is left unconnected, WDO can be used as
a low-line output. Since floating WDI disables
the internal timer, WDO goes LOW only when
V
CC
falls below the reset threshold, thus func-
tioning as a low-line output.
Figure 14. SP705/706/813L/813M Watchdog Timing Waveforms
Figure 15. SP705/706 Timing Diagrams with WDI Tri-stated. The SP707/708/813L/813M RESET Output is the Inverse
of the RESET Waveform Shown.
t
RS
RESET*
WDO
0V
+5V
WDI
RESET*
0V
+5V
0V
+5V
0V
+5V
t
WD
t
WD
t
WD
t
WP
* externally triggered LOW by MR,
RESET is for the SP813L/813M only
V
CC
RESET
0V
+5V
0V
+5V
0V
+5V
t
RS
t
RS
t
MR
0V
+5V
MR*
WDO
V
RT
V
RT
*externally driven LOW
t
MD
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