參數(shù)資料
型號: SP708TEN
英文描述: +3.0V/+3.3V Low Power Microprocessor Supervisory Circuits
中文描述: 3.0V / 3.3V低功耗微處理器監(jiān)控電路
文件頁數(shù): 12/18頁
文件大?。?/td> 213K
代理商: SP708TEN
12
Rev. 10-17-00 SP706 +3.0/ +3.3 Low Power Microprocessor Circuits Copyright 2000 Sipex Corporation
Ensuring a Valid RESET Output Down to
V
CC
= 0V
When V
falls below 1V, the RESET output no
longer sinks current, it becomes an open circuit.
High-impedance CMOS logic inputs can drift to
undetermined voltages if left undriven. If a pull-
down resistor is added to the RESET pin, any
stray charge or leakage currents will be shunted
to ground, holding RESET LOW. The resistor
value is not critical. It should be about 100K
,
large enough not to load RESET and small
enough to pull RESET to ground.
Monitoring Voltages Other Than the
Unregulated DC Input
Monitor voltages other than the unregulated DC
by connecting a voltage divider to PFI and
adjusting the ratio appropriately. If required,
add hysteresis by connecting a resistor (with a
value approximately 10 times the sum of the
two resistors in the potential divider network)
between PFI and PFO. A capacitor between PFI
and GND will reduce the power-fail circuit's
sensitivity to high-frequency noise on the
line being monitored. RESET can be used to
monitor voltages other than the +3.3V/+3.0V
V
line. Connect PFO to MR to initiate a
RESET pulse when PFI drops below 1.25V.
Figure 17
shows the SP706R/S/T-SP708R/
S/T series configured to assert RESET when the
+3.3V/+3.0V supply falls below the RESET
threshold, or when the +12V supply falls below
approximately 11V.
Monitoring a Negative Voltage Supply
The power-fail comparator can also monitor a
negative supply rail, shown in
Figure 18
.
When the negative rail is good (a negative
voltage of large magnitude), PFO is LOW. By
adding the resistors and transistor as shown, a
HIGH PFO triggers RESET. As long as PFO
remains HIGH, the
SP706P/R/S/T-SP708R/S/
T series will keep RESET asserted (where
RESET = LOW and RESET = HIGH). Note that
this circuit's accuracy depends on the PFI
threshold tolerance, the V
CC
line, and the resis-
tors.
Interfacing to mPs with Bidirectional
RESET Pins
μ
Ps with bidirectional RESET pins, such as the
Motorola 68HC11 series, can contend with the
RESET output. If, for example, the RESET
PFI
PFO
V
CC
+3.3V/+3.0V
GND
RESET
to
μ
P
MR
+12V
1M
1%
130K
1%
Figure 17. Monitoring Both +3.3V/+3.0V and +12V
Power Supplies
GND
GND
RESET
INTERRUPT
I/O LINE
NMI
V
CC
RESET
PFO
PFI
R
2
R
1
Unregulated DC
Power Supply
Regulated +3.3V/+3.0V
Power Supply
V
CC
0.1
μ
F
PFI
μ
P
WDO
PUSHBUTTON
SWITCH
MR
Figure 16. Typical Operating Circuit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SP708TEN-L 功能描述:監(jiān)控電路 LOW PWR MICROPROCESSOR RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
SP708TEN-L/TR 功能描述:監(jiān)控電路 LOW PWR MICROPROCESSOR RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
SP708TEP 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:+3.0V/+3.3V Low Power Microprocessor Supervisory Circuits
SP708TEU 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:+3.0V/+3.3V Low Power Microprocessor Supervisory Circuits
SP710AS 制造商:Rochester Electronics LLC 功能描述:- Bulk