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參數(shù)資料
| 型號(hào)： | SP7653TR |
| 英文描述： | Wide Input Voltage Range, 1.3MHz,Buck Regulator |
| 中文描述： | 寬輸入電壓范圍，1.3MHz，降壓穩(wěn)壓器 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 207K |
| 代理商： | SP7653TR |
9
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator Copyright 2005 Sipex Corporation
APPLICATIONS INFORMATION
The capacitor type suitable for the output capac-
itors can also be used for the input capacitors.
However, exercise extra caution when tantalum
capacitors are used. Tantalum capacitors are known
for catastrophic failure when exposed to surge
current, and input capacitors are prone to such
surge current when power supplies are connected
“l(fā)ive” to low impedance power sources. Although
tantalum capacitors have been successfully em-
ployed at the input, it is generally not recom-
mended.
Loop Compensation Design
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the desired frequency cut-off (FCO), the
gain of the error amplifier has to compensate for
the attenuation caused by the rest of the loop at
this frequency. The goal of loop compensation
is to manipulate loop frequency response such
that its cross-over gain at 0db, results in a slope
of -20db/dec.
The first step of compensation design is to pick
the loop cross over frequency. High cross over
frequency is desirable for fast transient response,
but often jeopardizes the power supply stability.
Cross over frequency should be higher than the
ESR zero but less than 1/5 of the switching
frequency or 60kHz. The ESR zero is contrib-
uted by the ESR associated with the output
capacitors and can be determined by:
Z(ESR)
=
1
2
π
C
OUT
R
ESR
The next step is to calculate the complex conju-
gate poles contributed by the LC output filter,
P(LC)
=
1
2
π
L C
OUT
When the output capacitors are of a Ceramic
Type, the SP7653 Evaluation Board requires a
Type III compensation circuit to give a phase
boost of 180
°
in order to counteract the effects of
an under damped resonance of the output filter
at the double pole frequency.
SP7653 Voltage Mode Control Loop with Loop Dynamic
Definitions:
R
ESR
= Output Capacitor Equivalent Series Resistance
R
DC
= Output Inductor DC Resistance
R
RAMP_PP
= SP7653 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
(SRz2Cz2+1)(SR1Cz3+1)
(SR
ESR
C
OUT
+ 1)
[S^2LC
OUT
+S(R
ESR
+R
DC
) C
OUT
+1]
V
IN
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
V
RAMP_PP
V
OUT
(Volts)
+
_
V
REF
(Volts)
Notes: R
ESR
= Output Capacitor Equivalent Series Resistance.
R
DC
= Output Inductor DC Resistance.
V
RAMP_PP
= SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> R
ESR
& R
DC
R
2
V
REF
V
OUT
(R
1
+ R
2
)
or
V
FBK
(Volts)
Type III Voltage Loop
Compensation
G
AMP
(s) Gain Block
PWM Stage
G
PWM
Gain
Block
Output Stage
G
OUT
(s) Gain
Block
Voltage Feedback
G
FBK
Gain Block
C
Z
2 >> Cp1 and R1 >> Rz3
Output Load Resistance >>
R
ESR
and
R
DC
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