參數(shù)資料
型號(hào)： SP7800AKN
英文描述： 12-Bit 3ms Sampling A/D Converter
中文描述： 12位為3ms采樣A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 10/13頁(yè)
文件大?。?/td> 171K
代理商： SP7800AKN
SP7800ADS/02
SP7800A 12-Bit 3
μ
s Sampling A/D Converter
10
Copyright 2000 Sipex Corporation
SYMBOL/PARAMETER
MIN
TYP
MAX
UNITS
t
W
t
DBC
t
B
t
AP
t
AP
t
C
t
DBE
t
DB
t
A
t
A
+ t
C
t
HDR
t
S
t
H
t
DD
R/C Pulse Width
BUSY delay from R/C
BUSY LOW
Aperture Delay
Aperture Jitter
Conversion Time
BUSY from End of Conversion
BUSY Delay after Data Valid
Acquisition Time
Throughput Time
Valid Data Held After R/C LOW
CS or HBE LOW before R/C Falls
CS or HBE LOW after R/C Falls
Data Valid from CS LOW, R/C HIGH, and HBE
in Desired State (Load = 100pF)
Delay to Hi-Z State after R/C Falls or
CS Rises (3K
Pullup or Pulldown
All parameters Guaranteed By Design
40
10
80
2.47
13
150
2.5
100
75
130
ns
ns
μ
s
ns
150
2.7
ps, rms
2.70
μ
s
ns
ns
ns
μ
s
ns
ns
ns
ns
25
200
300
3.0
20
25
25
50
5
0
65
150
t
HL
50
150
ns
AC DYNAMIC TIMING DATA
Figure 7. Conversion Start Timing
R/C
BUSY
Data
BUS
CS or
HBE
Data Valid
Hi-Z State
t
S
t
H
t
W
t
DBC
t
HDR
and t
HL
tions, the multiplexer can be switched as soon as R/C
goes LOW (with appropriate delays), but this may
affect the conversion if the switched signal shows
glitches or significant ringing at the
SP7800A
input.
Whenever possible, it is safer to wait until the conver-
sion is completed before switching and multiplexer.
The extremely fast acquisition time and conversion
time of the
SP7800A
make this practical in many
applications.
Naturally, transients on the analog input signal are to
be avoided, especially at times within
±
20ns of R/C
going LOW, when they may be trapped as part of the
charge on the capacitor array. This requires careful
layout of the circuit in front of the
SP7800A.
Finally, in multiplexed systems, the timing relative to
when the multiplexer is switched may affect the
analog performance of the system. In most applica-
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參數(shù)描述
SP7800AKS 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit 3ms Sampling A/D Converter
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