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參數(shù)資料
| 型號(hào)： | SP791EN |
| 英文描述： | Low Power Microprocessor Supervisory with Battery Switch-Over |
| 中文描述： | 低功耗微處理器監(jiān)控與電池開關(guān)過(guò) |
| 文件頁(yè)數(shù)： | 9/19頁(yè) |
| 文件大?。?/td> | 202K |
| 代理商： | SP791EN |
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9
SP791DS/08 SP791 Low Power Microprocessor Supervisory with Battery Switch-Over
Copyright 2000 Sipex Corporation
MR low for a minimum of 25
μ
s resets all the
internal counters, sets the Watchdog Output
(WDO) and Watchdog-Pulse Output (WDPO)
high, and sets the Set Watchdog-Timeout (SWT)
input to V
OUT
if it is not already connected to
V
OUT
(for Internal timeouts). It also, disables
the Chip-Enable Output (CE
OUT
) forcing it to
a high state. The RESET output remains at a
logic low as long as MR is held low, and the
reset-timeout period begins after MR returns
high,
Figure 2
.
Use this input as either a digital-logic input or a
second low-line comparator. Normal TTL/
CMOS levels can be wire-OR connected via
pull-down diodes,
Figure 3
, and open-drain/col-
lector outputs can be wire-ORed directly.
RESET OUTPUT
The
SP791's
RESET output ensures that the
μ
P
powers up in a known state, and prevents code-
execution errors during power-down or brown-
out conditions.
The RESET output is active low, and typically
sinks 3.2mA at 0.1V saturation voltage in its
active state. When deasserted, RESET sources
1.6mA at V
OUT
– 0.5V. When no backup bat-
tery is used, RESET output is valid down to V
CC
= 1V, and an external 10k
pull-down resistor
on RESET ensures that RESET will be valid
with V
CC
down to GND as shown on
Figure 4
.
As V
CC
goes below 1V, the gate drive to the
RESET output switch reduces accordingly,
increasing the r
(ON) and the saturation volt-
age. The 10k
pull-down resistor ensures the
parallel combination of switch and external
resistor is 10k
and the output saturation volt-
age is below 0.4V, while sinking 40
μ
A. When
using a 10k
external pull-down resistor, the
high state for the RESET output with Vcc =
4.75V is 4.5V typical. For battery voltages
greater than or equal to 2V, RESET remains
valid for V
CC
between 0V and 5.5V. RESET will
be asserted during the following conditions:
1) V
CC
< 4.65V (typ)
2) MR < 1.25V (typ)
3) RESET = logic "0" ; for 200 ms (typ) after
Vcc rises above 4.65V or after MR has exceeded
1.25V.
The
SP791
battery-switchover comparator does
not affect RESET assertion.
Figure 5. WDI, WDO and WDPO Timing
Diagram (V
CC
mode).
Figure 4. Adding an external pull-down resistor ensures
RESET is valid with V
CC
down to GND.
Figure 6. Two consecutive watchdog faults latch the system in reset.
TO
μ
P RESET
10k
15
C orporation
RESET
1.6sec
100ns MIN
WDI
WDPO
WDO
70ns
C orporation
Vcc
V
BATT
V
OUT
RESET
WDI
LOWLINE
WDPO
WDO
GND
4
MR
3.6V
1
3
2
15
11
10
16
14
9
4.7k
*
1
μ
F
+5V
REACTIVATE
CLOCK
D
SET
Vcc
CD4013
RESET
Vss
Q
Q
2
1
14
3
6
5
4
7
1/6 74HC04
TWO
μ
P POWER
μ
P
RESET
I/O
NMI
INTERRUPT
0.1
μ
F
+5V
SETS Q HIGH ON POWER-UP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP791EN-L | 功能描述:監(jiān)控電路 LW PWR MICRO 5.5V 25mA-250mA BAT SW/OV RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP791EN-L/TR | 功能描述:監(jiān)控電路 LW PWR MICRO 5.5V 25mA-250mA BAT SW/OV RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| SP791EP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Low Power Microprocessor Supervisory with Battery Switch-Over |
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