參數(shù)資料
型號: SP800LCT
英文描述: Low Power Microprocessor Supervisory with Battery Switch-Over
中文描述: 低功耗微處理器監(jiān)控與電池開關(guān)過
文件頁數(shù): 17/24頁
文件大?。?/td> 196K
代理商: SP800LCT
Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over Copyright 2004 Sipex Corporation
17
and connect CE
to the CE input of each
memory device as shown in
Figure 26
. The CE
input of each part then connects directly to the
chip-select logic, which does not have to gated
by the
SP691A/693A/800L/800M
devices.
Adding Hysteresis to the Power-Fail
Comparator
Hysteresis adds noise margin to the power-fail
comparator and prevents repeated triggering of
PFO when V
is near the power-fail comparator
trip point.
Figure 27
shows how to add hysteresis
to the power-fail comparator. Select the ratio of
R1 and R2 such that PFI sees 1.25V when V
IN
falls to the desired trip point (V
). Resistor
R3 adds hysteresis. It will typically be an order
of magnitude greater than R1 or R2. The
current through R1 and R2 should be at least
1
μ
A to ensure that the 25nA (max) PFI input
current does not shift the trip point. R3 should
be larger than 10k
to prevent it from loading
down the PFO pin. Capacitor C1 adds additional
noise rejection.
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor
a negative supply voltage using the circuit shown
in
Figure 28
. When the negative supply is valid,
PFO is low. When the negative supply voltage
drops, PFO goes high. This circuit's accuracy is
affected by the PFI threshold tolerance, the V
CC
voltage, and resistors R1 and R2.
Backup-Battery Replacement
The backup battery may be disconnected while
V
CC
is above the reset threshold. No precautions
are necessary to avoid spurious reset pulses.
Figure 26. Alternate Chip Enable Gating
GND
V
OUT
R
P
*
2
CE
CE
CE
CE
CE
CE
CE
CE
Active-HIGH
CE Logic Lines
for Memory Devices
CE
OUT
CE
IN
13
4
12
*
P
is dependent
.
P
Minimum value of R
RAM
1
RAM
2
RAM
3
RAM
n
Figure 27. Adding Hysteresis to the Power-Fail
Comparator
PFI
PFO
R
3
*C
1
R
2
R
1
V
IN
connect to
μ
P
V
CC
+5V
GND
PFO
V
IN
+5V
0V0V
V
L
V
H
V
TRIP
*optional
V
TRIP
=
R
R
1
+ R
2
V
H
=
R
2
|| R
3
R
1
+ R
2
|| R
3
1.25
R
2
=V
L
- 1.25
R
1
5.0 - 1.25
R
3
+
1.25
1.25
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