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| 型號： | SP800M |
| 英文描述： | Low Power Microprocessor Supervisory with Battery Switch-Over |
| 中文描述： | 低功耗微處理器監(jiān)控與電池開關(guān)過 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 196K |
| 代理商： | SP800M |
Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over Copyright 2004 Sipex Corporation
13
RESET and RESET are asserted for the reset
timeout period (200ms nominal). WDO goes
to logic low and remains low until the next
transition at WDI. Refer to
Figure 20
. If WDI
is held high or low indefinitely, RESET and
RESET will generate 200ms pulses every 1.6s.
WDO has a 2 x TTL output characteristic.
Selecting an Alternative Watchdog
Timeout Period
The OSC
and OSC
inputs control the
watchdog are reset timeout periods. Floating
OSC
and OSC
or tying them both to V
selects the nominal 1.6s watchdog timeout
period and 200ms reset timout period.
Connecting OSC
IN
to ground and floating or
connecting OSC
to V
selects a 100ms nor-
mal watchdog timeout period and a 1.6s timeout
period immediately after reset. The reset timeout
period remains 200ms. Refer to
Figure 20
.
Select alternative timeout periods by connecting
OSC
to ground and connecting a capacitor
between OSC
and ground, or by externally
driving OSC
. A synopsis of this control can
be found in
Figure 21
and
Table 1
.
Chip-Enable Signal Gating
The
SP691A/693A/800L/800M
devices
provide internal gating of chip-enable (CE)
signals, to prevent erroneous data from
corrupting the CMOS RAM in the event of a
power failure. During normal operation, the CE
gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes
disabled, preventing erroneous data from
corrupting the CMOS RAM. The
SP691A/
693A/800L/800M
devices use a series transmission
gate from CE
IN
to CE
OUT
. Refer to
Figure 16.
The 10ns maximum CE propagation from CE
IN
to CE
OUT
enables the
SP691A/693A/800L/
800M
μ
Ps.
Chip-Enable Input
CE
is in high impedance (disabled mode)
while RESET and/or RESET are asserted.
During a power-down sequence where V
falls
below the reset threshold, CE
assumes a high
impedance state when the voltage at CE
goes
high or 12
μ
s after RESET is asserted,
whichever occurs first. Refer to
Figure 19
.
During a power-up sequence, CE
remains high
impedance until RESET is deasserted.
In the high-impedance mode, the leakage
currents into CE
are <1
μ
A over temperature.
In the low-impedance mode, the impedance of
CE
appears as a 65
resistor in series with
the load at CE
OUT
.
The propagation delay through the CE
transmission gate depends on both the source
impedance of the drive to CE
and the
capacitive loading on CE
(see the
Chip-Enable Propagation Delay vs. CE
Load Capacitance graph in the
Typical
Performance Characteristics
section
).
The
CE propagation delay is defined from the 50%
point on CE
to the 50% point on CE
using
a 50
driver and 50pF of load capacitance as in
Figure 22
. For minimum propagation delay,
minimize the capacitive load at CE
OUT
and use
a low output-impedance driver.
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Table 1. Reset Pulse Width and Watchdog Timeout Selections
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