參數(shù)資料
型號(hào): SP800MEN
英文描述: Datamate J-Tek DIL Male Horizontal 4.5mm PC Tail Connector, selective gold + tin, with jackscrews, 21+21-way
中文描述: 低功耗微處理器監(jiān)控與電池開關(guān)過
文件頁(yè)數(shù): 9/24頁(yè)
文件大?。?/td> 196K
代理商: SP800MEN
Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over Copyright 2004 Sipex Corporation
9
Pin 12 — CE
— Chip-Enable Output. This
output pin goes LOW only when CE
is
LOW and V
is above the reset threshold
voltage. If CE
is LOW when RESET is
asserted, this output pin will stay low for
16
μ
s or until CE
IN
goes HIGH, whichever
occurs first.
Pin 13 — CE
— Chip-Enable Input. This is the
input pin to the chip-enable gating circuit.
If this input pin is not used, connect it to
ground or V
OUT
.
Pin 14 — WDO — Watchdog Output. If WDI
remains HIGH or LOW longer than the
watchdog timeout period, this output pin
goes LOW and RESET is asserted for the
reset timeout period. This output pin returns
HIGH on the next transition at WDI.
This output pin remains HIGH if WDI is
unconnected.
Pin 15 — RESET — Active LOW Reset Output.
This output pin goes LOW whenever V
falls below the reset threshold. This output
pin will remain low typically for 200ms after
V
crosses the reset threshold voltage on
power-up.
Pin 16 — RESET — Active HIGH Reset
Output. This output pin is open drain and
the inverse of RESET.
Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M
OSC
IN
4
1.25V
Reset
Generator
CE
Control
Watchdog
Timer
Reset /
Watchdog
Timebase
Watchdog
Transition
Detector
WDI
OSC
SEL
V
CC
V
BATT
BATT ON
CE
IN
CE
OUT
V
OUT
LOWLINE
RESET
RESET
PFO
PFI
9
11
8
7
3
1
5
13
12
GND
2
6
16
15
4.65V or
4.40V*
WDO
14
10
4.65V for the
SP691A/800L
4.40V for the
SP693A/800M
*
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