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| 型號(hào)： | SP800MEP |
| 英文描述： | Low Power Microprocessor Supervisory with Battery Switch-Over |
| 中文描述： | 低功耗微處理器監(jiān)控與電池開關(guān)過 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 196K |
| 代理商： | SP800MEP |
Date: 5/25/04 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over Copyright 2004 Sipex Corporation
12
Watchdog Function
The watchdog monitors
μ
P activity via the
Watchdog Input (WDI). If the
μ
P becomes
inactive, RESET and RESET are asserted
.
To use the watchdog function, connect WDI to
a bus line or
μ
P I/O line. If WDI remains high
or low for longer than the watchdog timeout pe-
riod (1.6s nominal). WDO, RESET, and RESET
are asserted, indicating a software fault or idle
conditions. Refer to
RESET and RESET
Outputs
and
Watchdog Output
sections.
Watchdog Input
A change of logic state (minimum 100ns
duration) at WDI during the watchdog period
will reset the watchdog timer. The watchdog
default timout is 1.6sec.
To disable the watchdog function, leave WDI
floating. An internal resistor network (100k
equivalent impedance at WDI) biases WDI to
approximately 1.6V. Internal comparators
detect this level and disable the watchdog timer.
When Vcc is below the reset threshold, the
watchdog function is disabled and WDI is
disconnected from its internal resistor network,
thus becoming high impedance.
Watchdog Output
WDO remains high if there is activity (transition
or pulse) at WDI during the watchdog-timeout
period. The watchdog function is disabled and
WDO is a logic high when V
CC
is less than the
reset threshold or when WDI is an open circuit.
In watchdog mode, if no transition occurs at
WDI during the watchdog-timeout period,
Figure 20. Watchdog Timeout Period and Reset Active Time
Figure 21. Selecting Timeout Periods
OSC
SEL
No Connect
X
No Connect
X
OSC
IN
7
8
OSC
SEL
No Connect
X
OSC
IN
7
8
OSC
SEL
OSC
IN
7
8
OSC
SEL
OSC
IN
7
8
1.6sec Normal Watchdog Timeout
Internal Oscillator
100ms Normal Watchdog Timeout
Internal Oscillator
Normal Watchdog Timeout = 647pF
External Oscillator
Normal Watchdog Timeout = 1024 Clock Periods
External Clock
IN
C
IN
t
2
t
1
t
1
t
3
t
1
= RESET Timeout Period
t
2
= Normal Watchdog Timeout Period
t
3
= Watchdog Timeout Period Immediately After RESET
WDI
WDO
RESET
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