參數(shù)資料
型號: SP8034A
英文描述: 250 V/us APC Amplifier with Integrated Photodiode and Gain Adjust Capability
中文描述: 250伏/我們apc的集成光電二極管放大器和增益調(diào)整能力
文件頁數(shù): 4/6頁
文件大小: 68K
代理商: SP8034A
4
Rev. 5/14/03
SP8034A APC Amplifier with Integrated Photodetector
Copyright 2003 Sipex Corporation
A major consideration in developing the optical
pick-up head system is the extremely small form
factor, which is additionally aggravated by the
physical locations required by the light path.
Special care must be taken when designing the
Flex or PCB for this part. The output peak
current requirement is in the order of 12.5 mA
when driving 50pF of capacitive load with a
slew rate of 250V/
μ
s. Therefore care must be
taken to provide low inductance, low resistance
paths for power and ground and output traces.
Supply coupling is also very important. Good
supply decoupling is important to ensure the
high frequency performance of the system by
eliminating supply lead inductance effects. The
decoupling capacitor C1, as shown in Figure 5,
should be as close to the part as possible.
This capacitor should be 0.1
μ
F ceramic. C2 is
optional to improve decoupling and is recom-
mended to be 1
μ
F tantalum. The layout of the
PCB is pictured here. Note the wide and short
traces on the supply lines.
The traces for the gain resistors R
GAIN
1 and
R
GAIN
2 are kept as short as possible to avoid
excessive parasitics. Any parasitics on these
nodes will limit the performance of the system.
R
GAIN
1 and R
GAIN
2 are subminiature potenti-
ometers in the application. This is a single layer
board using FR4 material.
In order to minimize coupling capacitance into
the gain setting resistor nodes, it is also critical
that V
OUT
+ and V
OUT
- are routed away from the
traces associated with the gain-setting resistors.
1
2
3
4
8
7
6
5
V
CC
GAIN
R
GCOM
GND
V
OUT
V
REF
R
GAIN2
R
GAIN1
R
G1
400
R
G1
400
RL
1k
C2
0.1
μ
F
+
+
CL1
50pF
RS
Depends
on FPC
V
REF
V
OUT
+
C1
0.1
μ
F
GAIN
+5V
SP8034A
Figure 5. Test Circuit - Cload = 50p, V
CC
= 5V, Gain = 0V, Rgain = 400.
V
CC
GAIN
GND
GND
V
O
RL
R2
R1
V
REF
CR
C
C
C
PIN
Figure 4. Evaluation Board.
LAYOUT AND ROUTING CONSIDERATIONS
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