參數(shù)資料
型號(hào): SP805TCN
英文描述: 3.0V/3.3V Low Power Microprocessor Supervisory with Battery Switch-Over
中文描述: 3.0V/3.3V低功耗微處理器監(jiān)控與電池開關(guān)過
文件頁(yè)數(shù): 13/20頁(yè)
文件大?。?/td> 233K
代理商: SP805TCN
13
SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
Copyright 2000 Sipex Corporation
The watchdog timer can also initiate a reset.
Refer to the
Watchdog Input
section.
The
SP804T/S/R
and
SP805T/S/R
active-HIGH
RESET output is open drain and the inverse
of the
SP690T/S/R
and
SP802T/S/R
RESET
outputs.
RESET is also triggered by a watchdog timeout.
If WDI remains either high or low for a period
that exceeds the watchdog timeout period (1.6
sec), RESET pulses low for 200mS. As long as
RESET is asserted, the watchdog timer remains
cleared. When RESET comes high, the watch-
dog resumes timing and must be serviced within
1.6sec. If WDI is tied high or low, a RESET
pulse is triggered every 1.8sec (t
WD
plus t
RS
).
Reset Threshold
The
SP690T
and
SP805T
devices are designed
for 3.3V systems with a
±
5% power-supply
tolerance and a 10% system tolerance. Except
for watchdog faults, reset will not assert as long
as the power supply remains above 3.15V (3.3V
- 5%). Reset is guaranteed to assert before the
power supply falls below 3.0V.
The
SP690S
and
SP805S
devices are designed
for 3.3V
±
10% power supplies. Except for
watchdog faults, they are guaranteed not to
assert reset as long as the supply remains above
3.0V (3.3V - 10%). Reset is guaranteed to
assert before the power supply fails below 2.85V
(V
CC
- 14%).
The
SP690R
and
SP805R
devices are optimized
for monitoring 3.0V
±
10% power supplies. Reset
will not occur until V
falls below 2.7V (3.0V
- 10%), but is guaranteed to occur before the
supply falls below 2.55V (3.0V - 15%).
The
SP802T/S/R
and
SP804T/S/R
devices are
respectively similar to the
SP690T/S/R
and
SP805T/S/R
devices with tightened reset
and power-fail threshold tolerances.
Watchdog Input
The watchdog circuit monitors the
μ
P's activity.
If the
μ
P does not toggle the watchdog input
(WDI) within 1.6sec, a reset pulse is triggered.
The internal 1.6sec timer is cleared by either a
reset pulse or by a transition (LOW-to-HIGH or
HIGH-to-LOW) at WDI. If WDI is tied HIGH
or LOW, a RESET pulse is triggered every
1.8sec (t
WD
plus t
RS
).
As long as reset is asserted, the timer remains
cleared and does not count. As soon as reset is
de-asserted, the timer starts counting. Unlike
the 5V
SP690A
series, the watchdog function
cannot
be disabled.
Power-Fail Comparator
The power-fail comparator can be used as an
under-voltage detector to signal the failing of a
power supply (it is completely separate from the
rest of the circuitry and does not need to be
dedicated to this function). The PFI input is
compared to an internal 1.25V. If PFI is less than
V
PFT
, PFO goes low.
The power-fail comparator turns off and PFO
goes LOW when V
falls below V
on
power-down. The power-fail comparator turns
on as V
crosses V
on power-up. If the
comparator is not used, connect PFI to ground
and leave PFO unconnected.
Backup-Battery Switchover
In the event of a brownout or power failure, it
may be necessary to preserve the contents of
RAM. With a backup battery installed at
V
, the devices automatically switch
RAM to backup power when V
CC
fails.
This family of
μ
P supervisors (designed for
3.3V and 3V systems) doesn't always connect
V
to V
OUT
when V
is greater
than V
. V
connects to V
(through
a 15
switch) when V
is below V
SW
and
V
BATTERY
is greater than V
CC
.
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