參數資料
型號: SP8121JP
英文描述: Monolithic, 12-Bit Data Acquisition System
中文描述: 單片,12位數據采集系統(tǒng)
文件頁數: 8/13頁
文件大?。?/td> 168K
代理商: SP8121JP
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
8
Copyright 2000 Sipex Corporation
R/C
STATUS
DB
11
- DB
0
t
HRH
t
C
DATA VALID
t
HDR
t
DDR
t
DS
HIGH–Z
HIGH–Z
HIGH PULSE FOR R/C DYNAMIC CHARACTERISTICS
V
CC
= +15V; V
LOGIC
= +5V; T
A
= 25
°
C
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
t
HRH
High R/C Pulse Width
t
DS
STATUS Delay from R/C
t
C
Conversion Time
t
DDR
Data Access Time
t
HDR
Data Valid after R/C Low
25
ns
200
ns
13
25
μ
s
T
MIN
to T
MAX
150
ns
25
ns
Figure 5. High Pulse for R/C — Outputs Enabled While R/C is High, Otherwise High Impedance
Figure 6. Low Pulse for R/C
R/C
STATUS
DB
11
- DB
0
t
HRL
t
C
DATA VALID
DATA VALID
t
MDH
t
DS
t
HDR
t
HS
MA
0
- MA
2
t
MDS
LOW PULSE FOR R/C DYNAMIC CHARACTERISTICS
V
CC
= +15V; V
LOGIC
= +5V; T
A
= 25
°
C
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
t
HRL
Low R/C Pulse Width
t
DS
Status Delay from R/C
t
HDR
Data Valid after R/C
t
HS
Status Delay after Data Valid 500
t
MDS
MUX Data Setup
t
MDH
MUX Data Valid
50
ns
200
ns
25
ns
ns
50
ns
3
10
μ
s
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