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參數(shù)資料
| 型號(hào)： | SP8121KS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-32 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 168K |
| 代理商： | SP8121KS |
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
Copyright 2000 Sipex Corporation
5
FEATURES
The SP8121 is a complete data acquisition systems,
featuring 8-channel multiplexer, internal reference
and 12-bit sampling A/D converter implemented as a
single monolithic IC. The analog multiplexer accepts
0V to +5V unipolar full scale inputs. Output data is
formatted in 12-bit parallel.
Linearity errors of +0.5 and +1.0 LSB, and Differen-
tial Non-linearity to 12-bits is guaranteed, with no
missing codes over temperature. Channel-to-channel
crosstalk is typically -85dB. Multiplexer settling plus
acquisition time is 1.9
s maximum; A/D conversion
time is 8.1
s maximum.
The SP8121 is available in a 32-pin plastic DIP or
SOIC packages. Operating temperature range is 0
°C
to +70
°C commercial.
The SAR, timed by the clock, sequences through the
conversion cycle and returns an end–of–convert flag
to the control section of the ADC. The clock is then
disabled by the control section, which puts the STA-
TUSoutputlinelow.Thecontrolsectionisenabledto
allow the data to be read by external command (R/C).
MULTIPLEXER CONTROL
On the SP8121 the address lines MA0, MA1, and
MA2 are latched into the internal address decode
circuitrywiththefallingedgeofLATCH.Dataset-up
time for these inputs is >=50nS. The MUX address
data must remain valid for the current conversion for
a minimum of 3.0
Saftertheconversionisinitiated.
ThisisthetimerequiredfortheMUXandSampleand
Hold to settle. However it is advisable that the MUX
not be changed at all during the full 10
S conversion
timeduetocapacitivecouplingeffectsofdigitaledges
through the silicon.
TheSP8121multiplexerinputshavebeendesignedto
allow substantial overvoltage conditions to occur
without any damage. The inputs are diode-clamped
and further protected with a 200
series resistor. As
a result, momentary (10 seconds) input voltages can
be as low as -16.5V or as high as +31.5V with no
change or degradation in multiplexer performance or
crosstalk. This feature allows the output voltage of an
externallyconnectedopamptoswingto+15Vsupply
levels with no multiplexer damage. Complicated
power-up sequencing is not required to protect the
SP8121. The multiplexer inputs may be damaged,
however, if the inputs are allowed to either source or
sink greater than 100mA.
INITIATING A CONVERSION
The SP8121 was designed to require a minimum of
control to perform a 12-bit conversion. The control
input used are R/C which tri-states the outputs when
high and starts the conversion when low, in combina-
tionwithCE.Thelastofthecontrolinputstoreachthe
correctstatestartstheconversion,thereforeeithermay
be dynamically controlled. The nominal delay from
each is the same and they may change state simulta-
neously. In order to ensure that a particular input
controls the conversion, the other should be set up at
least 50ns earlier. The STATUS line indicates when
a conversion is in process and when it is complete.
CIRCUIT OPERATION
The SP8121 is a complete 8-channel data acquisition
systems (DAS), with on-board multiplexer, voltage
reference, sample-and-hold, clock and tri-state
outputs.Thedigitalcontrolarchitectureisverysimilar
to the industry-standard 574-type A/D, and uses
identical control lines and digital states.
The multiplexer for the SP8121 is identical in
operation to many discrete devices available today,
except that it has been integrated into the single-chip
DAS. The appropriate channel is selected using the
MUXaddresslinesMA
0, MA1, and MA2 per the truth
table. The selected analog input is fed through to the
ADC. The input impedance into any MUX channel
will be on the order to 109 ohms, since it is connected
to the integral sampling structure of the capacitor
DAC.Crosstalkiskeptto-85dBat0Vto5V
p-p over an
input frequency range of 10kHz to 50kHz.
When the control section of the SP8121 initiates a
conversion command the internal clock is enabled,
and the successive approximation register (SAR) is
resettoallzeros.Oncetheconversionhasbeenstarted
it cannot be stopped or restarted. Data is not available
at the output buffers until the conversion has been
completed.
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