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參數(shù)資料
| 型號(hào)： | SP8121KS |
| 英文描述： | CAP ELECT 1UF 50V KK RADIAL |
| 中文描述： | 單片，12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大小： | 168K |
| 代理商： | SP8121KS |
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SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
6
Copyright 2000 Sipex Corporation
SP8121
OFFSET ADJUST
100K
+15V
5K
–1.5mV to +3mV
6
Figure 1. Offset Adjust
SP8121
GAIN ADJUST
125K
+15V
10K
±0.3% Trim Range
7
19K
Center pot
Figure 2. Gain Adjust
The conversion cycle is started when R/C is brought
low and must be held low for a minimum of 50ns. The
R/C signal will also put the output latches in a tri-state
mode when low. Approximately 200ns after R/C is
low, STATUS will change from low to high. This
output signal will stay high while the
SP8121
is
performing a conversion. Valid data will be latched to
the output bus, through internal control, 500ns prior
to the STATUS line transitioning from a high to low.
READING THE DATA
Please refer to
Figure 4
. To read data from the
SP8121
, the R/C and CE control lines are used. R/C
must be high a minimum of 50ns prior to reading
the data to allow time for the output latches to come
out of the high impedance tri-state mode. CE is used
to access the data. The first 8 MSBs will be on
pins 32 through 25, with pin 32 being the MSB.
The remaining 4 LSBs will be on pins 21 through 24
with pin 21 being the LSB. When CE is switched
from one state to the next, there is a 50ns output
latch propagation delay between the MSBs and LSBs
being present on the output pins.
CALIBRATION
The calibration procedure for the
SP8121
consists of
adjusting the most negative input voltage (0V) to the
ideal output code for offset adjustment, and then
adjusting the most positive input voltage (5.0V) to its
ideal output code for gain adjustment.
Offset Adjustment
The offset adjustment must be completed first. Please
refer to
Figure 1
. Apply an input voltage of 0.5LSB or
610
μ
V to any multiplexer input. Adjust the offset
potentiometer so that the output code fluctuates evenly
between 000…000 and 000…001. It is only
necessary to observe the lower eight LSB’s during this
procedure.
Gain Adjustment
With the offset adjusted, the gain error can now be
trimmed to zero. (Please refer to
Figure 2
.) The ideal
input voltage corresponding to 1.5 LSB’s below the
nominal full scale input value, or +4.988V, is applied
to any multiplexer input. The gain potentiometer is
adjusted so that the output code alternates evenly
between 111…111 and 111…110. Again, only the
lower eight LSB’s need be observed during this
procedure. With the above adjustment made, the
converter is now calibrated.
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