- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372199 > SP8481 Monolithic, 12-Bit Data Acquisition System PDF資料下載
參數(shù)資料
| 型號： | SP8481 |
| 英文描述： | Monolithic, 12-Bit Data Acquisition System |
| 中文描述： | 單片，12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 211K |
| 代理商： | SP8481 |
305
FEATURES…
The
SP8481 Series
are complete data acquisi-
tion systems, featuring 8-channel multiplexer,
internal reference and 12-bit sampling A/D con-
verter implemented as a single monolithic IC.
The analog multiplexer accepts 0V to +5V uni-
polar full scale inputs. Output data is formatted
as an 8-bit/4-bit nibble.
Linearity errors of
±
0.5 and
±
1.0 LSB, and
Differential Non-linearity to 12-bits is guaran-
teed, with no missing codes over temperature.
Channel-to-channel crosstalk is typically -85dB.
Multiplexer settling plus acquisition time is 1.9
μ
s
maximum; A/D conversion time is 8.1
μ
s maxi-
mum.
Versions of the
SP8481 Series
are available in
32-pin plastic DIP or SOIC packages. Operating
temperature ranges are 0
°
C to +70
°
C commer-
cial and -40
°
C to +85
°
C industrial.
CIRCUIT OPERATION…
The
SP8481
is a complete 8-channel data acqui-
sition system (DAS), with on-board multiplexer,
voltage reference, sample–and–hold, clock and
tri–state outputs. The digital control architecture
is very similar to the industry-standard 574-type
A/D, and uses identical control lines and digital
states.
The multiplexer for the
SP8481
is identical in
operation to many discrete devices available
today, except that it has been integrated into the
single-chip DAS. The appropriate channel is
selected using the MUX address lines MA
0
,
MA
1
, and MA
2
per the truth table. The selected
analog input is fed through to the ADC. The
input impedance into any MUX channel will be
on the order to 10
9
ohms, since it is connected to
the integral sampling structure of the capacitor
DAC. Crosstalk is kept to -85dB at 0V to 5V
p-p
over an input frequency range of 10kHz to 50kHz.
When the control section of the
SP8481
initiates
a conversion command the internal clock is
enabled, and the successive approximation reg-
ister (SAR) is reset to all zeros. Once the conver-
sion has been started it cannot be stopped or
restarted. Data is not available at the output
buffers until the conversion has been completed.
The SAR, timed by the clock, sequences through
the conversion cycle and returns an end–of–
convert flag to the control section of the ADC.
The clock is then disabled by the control section,
which puts the STATUS output line low. The
control section is enabled to allow the data to be
read by external command (R/C).
Multiplexer Control and Inputs
On the
SP8481
the multiplexer inputs are latched
with LATCH. The address line latches MA
0
,
MA
1
and MA
2
select the appropriate analog
input channel. When low, the LATCH line re-
tains the last MUX address data, and therefore
the previously addressed MUX channel. All
channels may be deselected by bringing the
MAEN control line to a logic “1”. When this
control function is used, the analog input will be
connected to pin 8 or analog ground.
Since the MUX address latches are controlled by
the LATCH and MAEN control lines, MUX
channel select data need not be held by the bus
for any minimum period after the conversion has
been initiated. However it is advisable that the
MUX not be changed at all during the full 10
μ
s
conversion time due to capacitive coupling ef-
fects of digital edges through the silicon.
The
SP8481
multiplexer inputs have been de-
signed to allow substantial overvoltage condi-
tions to occur without any damage. The inputs
are diode-clamped and further protected with a
200
series resistor. As a result, momentary (10
seconds) input voltages can be as low as -16.5V
or as high as +31.5V with no change or degrada-
tion in multiplexer performance or crosstalk.
This feature allows the output voltage of an
externally connected op amp to swing to
±
15V
supply levels with no multiplexer damage. Com-
plicated power-up sequencing is not required to
protect the
SP8481
. The multiplexer inputs may
be damaged, however, if the inputs are allowed
to either source or sink greater than 100mA.
Initiating a Conversion
The
SP8481
was designed to require a minimum
of control to perform a 12-bit conversion. The
control input used is R/C which tri-states the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP8481AP | Monolithic, 12-Bit Data Acquisition System |
| SP8481AS | Monolithic, 12-Bit Data Acquisition System |
| SP8481BP | Monolithic, 12-Bit Data Acquisition System |
| SP8481BS | Monolithic, 12-Bit Data Acquisition System |
| SP8481JP | Monolithic, 12-Bit Data Acquisition System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP8481AP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Monolithic, 12-Bit Data Acquisition System |
| SP8481AS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Monolithic, 12-Bit Data Acquisition System |
| SP8481BP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Monolithic, 12-Bit Data Acquisition System |
| SP8481BS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Monolithic, 12-Bit Data Acquisition System |
| SP8481JP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Monolithic, 12-Bit Data Acquisition System |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。