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參數(shù)資料
| 型號(hào)： | SP8530BN |
| 元件分類： | ADC |
| 英文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | SP8530BN |
SP8530DS/01
SP8530 S2ADC
TM - Simultaneous Sampling Analog to Digital Converter
Copyright 2000 Sipex Corporation
2
ABSOLUTE MAXIMUM RATINGS
(TA=+25C unless otherwise noted) ..............................................
VDD to DGND ............................................................. -0.3V to +7V
VDA to AGND .............................................................. -0.3V to +7V
Vin to AGND .................................................... -0.3V to VDA +0.3V
Digital Input to VSS ........................................... -0.3V to VDD+0.3V
Digital Output to VSS ........................................ -0.3V to VDD+0.3V
Operating Temp. Range
Commercial (J,K Version) ............................... 0C to 70C
Industrial (A,B Version) .............................. -40C to +85C
Storage Temperature ............................................... -65C to 150C
Lead Temperature(Solder 10sec) ........................................ +300C
Power Dissipation to +70C ................................................ 500mW
Derate Above 70C ......................................................... 10mW/ C
SPECIFICATIONS
Unless otherwise noted the following specifications apply for V
DD = 5V with limits applicable for TA = 25
oC.
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
DC Accuracy
Resolution
12
Bits
Integral Linearity
J, A
+0.6
+1.0
LSB
K ,B
+0.4
+0.75
LSB
Differential Linearity Error
J, A
+0.5
+1.0
LSB
No Missing Codes
K ,B
+0.5
+1.0
LSB
No Missing Codes
Gain Error
J, A
+0.2
+1.0
%FSR
Externally Trimmable to Zero
K,B
+0.1
+0.5
%FSR
Externally Trimmable to Zero
Offset Error
J, A
+4
+7
LSB
Externally Trimmable to Zero
K,B
+3
+5
LSB
Externally Trimmable to Zero
Gain Match
J, A
+2
LSB
K,B
+2
LSB
Offset Match
J, A
+1.0
LSB
Externally Trimmable to Zero
K,B
+0.5
LSB
Externally Trimmable to Zero
Analog Input
0 to 2.5
Volts
Conversion Speed
Sample Time
400
ns
Conversion Time
7.75
s
Complete Cycle
8.25
Simultaneous Convert
Rate:
121
KHz
Simultaneous Pair
Clock Speed
4
MHz
Data Rate:
242
KHz
Total Data Conversion Rate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP8530KN | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP16 |
| SP8530BS | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| SP8530JS | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| SP8538KN | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8 |
| SP8538BS | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP8530BS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:S2ADC - Simultaneous Sampling Analog to Digital Converter |
| SP8530JN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:S2ADC - Simultaneous Sampling Analog to Digital Converter |
| SP8530JS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:S2ADC - Simultaneous Sampling Analog to Digital Converter |
| SP8530KN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:S2ADC - Simultaneous Sampling Analog to Digital Converter |
| SP8530KS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:S2ADC - Simultaneous Sampling Analog to Digital Converter |
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