SP8530DS/01 SP8530 S
2
ADC
TM
- Simultaneous Sampling Analog to Digital Converter
Copyright 2000 Sipex Corporation
6
The device responds to the shut down signal
asynchronously so that a conversion in progress
will be interrupted and the resulting data will be
erroneous. A 20
μ
Sec delay is required between
the falling edge of power down and initiation of
a conversion.
Data Format
32 bits of data are sent for each conversion. The
first 16 bits are the conversion A result, which is
shipped with 4 leading "0"s, and then 12 bits of
data, MSB first. The second 16 bits are the
conversion B result, which are also shipped with
4 leading "0"s, and then 12 bits of data, MSB
first. Data changes on the falling edge of SCLK
and is stable on the rising edge of SCLK.
Layout Considerations
Because of the high resolution and linearity of
the
SP8530
system design considerations such
as ground path impedance and contact
resistance become very important.
To avoid introducing distortion when driving
the analog inputs of these devices, the source
resistance must be very low, or constant with
signal level. Note that in the operating circuit
there is no connection made between VDA (Pin
12) and the system power supply. This is
because the analog supply pin (VDA) is
connected internally to the digital supply pin
(VDD) through a ten ohm resistor.
This connection when combined with parallel
combination of 6.8
μ
F tantalum and 0.1
μ
F
ceramic capacitor between VDA and analog
ground, will provide some immunity to noise
which resides on the system supply. To maintain
maximum system accuracy, the supply
connected to the VDD pin should be well
isolated from digital supplies and wide load
variations.
To limit effects of digital switching elsewhere
in a system, it often makes sense to run a
separate +5V supply conductor from the supply
regulator to any analog components requiring
+5V including the
SP8530
. Noise on the power
Continuous stand alone operation is obtained by
holding CS low. In this mode an oscillator is
connected directly to SCLK pin. The SCLK
signal along with the STATUS output Signal
are used to synchronize the host system with the
converter's data. In this mode there is a single
dead SCLK cycle between the 32nd clock of one
conversion and the first clock of the following
conversion for the
SP8530
. A clock frequency
of 4 MHz the
SP8530
provides a throughput
rate of 121KHz.
In slave mode operation, CS is brought high on
each conversion so that all conversions are
initiated by falling edge on CS.
Figure 1. Operating Circuit
16
15
14
13
12
11
10
9
GAIN ADJUST
REF OUT
OFFSET ADJ. B
OFFSET ADJ. A
SP8530
VDA
VDD
SHUTDOWN
CS
1
2
3
4
5
6
7
8
N.C.
VIN B
VIN A
AGND
VSS
SCLK
DOUT
STATUS
VA
+5V
CLOCK IN
DATA OUT
STATUS OUT
CHIP SELECT
SHUTDOWN
0.1μF
2kOhms
5kOhms
10kOhms
2kOhms
5kOhms
0.01μF*
6.8μF
0.1μF
VB
* Optional filter capacitor is helpful in a noisy pc board application.