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參數(shù)資料
| 型號： | SP8542JN |
| 元件分類： | ADC |
| 英文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 219K |
| 代理商： | SP8542JN |
SP8542/8544DS/01
SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's
Copyright 2000 Sipex Corporation
7
118
GAIN ADJUST
N.C.
217
REF OUT
CH0
415
514
OFFSET ADJ.
CH3
613
V
DA
V
SS
712
V
DD
SCLK
811
CS
D
OUT
910
STATUS
SP8544
CH2
STATUS OUT
DATA OUT
CLOCK IN
10kOhms
0.01
F*
* Optional filter capacitor is helpful in a noisy pc board application.
16
3
CH1
CH2
AGND
SD
DIN
DATA IN
CHIP SELECT
CH3
CH1
CH0
+5V
0.1
F
0.1
F
6.8
F
SHUT DOWN
2kOhms
5kOhms
+
Figure 2. Operating Circuit
These bits, if shifted in during the nth conversion,
will determine the input configuation for the
(n+1) conversion (see timing diagram). The
input range is 0 to 2.5V. The serial output is
Hi-Z unless conversion data is being shifted out.
It is therefore possible to tie the DIN pin to the
DOUT pin for a 3-wire interface or leave them
seperate for a 4-wire interface. The output is
compatible with SPI, QSPI and MICROWIRE
serial communication protocols.
0utput Data Format
12 Bits of data are sent in 16 clock cycles for
each conversion. Dout is in high impedance
state during the first four clock cycles of the
conversion and sends the 12 bits of data MSB
first, in the succeeding 12 clock cycles. Output
data changes on the falling edge of SCLK and is
stable on the rising edge of SCLK.
Free Running operation is obtained by holding
CS low. In this mode an oscillator is connected
directly to SCLK pin. The SCLK signal along
with the STATUS output Signal are used to
synchronize the host system with the converter's
data. In this mode there is a single dead SCLK
cycle between the 16th clock of one conversion
and the first clock of the following conversion
for both the SP8542 and SP8544. At a clock
frequency of 4 MHz the SP8542 provides a
throughput rate of 117.6KHz for both channels
and the SP8544 provides a throughput rate of
58.8KHz for all four channels. Both devices
provide a throughput rate of 235KHz for one
channel in Free Running Mode.
In slave mode operation, CS is brought high
between each conversion so that all conversions
are initiated by falling edge on CS.
Layout Considerations
Because of the high resolution and linearity of
the SP8542 and SP8544 system design
considerations such as ground path impedance
and contact resistance become very important.
To avoid introducing distortion when driving
the analog inputs of these devices, the source
resistance must be very low, or constant with
signal level. Note that in the operating circuit
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| SP8542JS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
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| SP8544AS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
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