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參數(shù)資料
| 型號(hào)： | SP8544KS |
| 英文描述： | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| 中文描述： | 雙和四通道12位多路采樣ADC |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 219K |
| 代理商： | SP8544KS |
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SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's
Copyright 2000 Sipex Corporation
9
TIMING CHARACTERISTICS
(Typical @ 25
°
C with V
DD
= +5V, unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNIT
COND.
Thoughput Time (tTP=tA+tC)
4.25
μ
s
Acquisition Time (tA) (2 SCLK Periods)
400
500
ns
Conversion Time (tC) (15 SCLK Periods)
3.75
μ
s
SCLKLow Pulse Width (tSKL)
110
125
ns
SCLK High Pulse Width (tSKH)
110
125
ns
SCLK Period (tSKT)
250
ns
Setup Time DIN to SCLK Rising (tDISU)
0
ns
Hold Time from SCLK Rising to DIN (tDIH).
5
ns
Buss Relinquish Time (tBR)
45
ns
Setup Time -SCLK Falling to CSN Falling (tCSSU)
10
ns
CSN Low Before SCLK Rises (tCS)
90
ns
SCLK Falling to Data Valid (tSD)
50
ns
CSN Falling to STATUS Rising (tDCS)
69
ns
SCLK 17Falling to Status Rising Free Run (tDSS)
70
ns
SCLK16 Falling to Status Falling ( tDSE)
45
ns
Delay SD Low to initiate Conversion (t
PU
)
5
μ
s
Aperture Delay Slave-Mode (tAPC)
30
ns
Aperture Delay Free-Running Mode (tAPS)
35
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP8544AS | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8542 | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8542BN | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8542BS | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
| SP8544JS | Two and Four Channel 12-Bit Multiplexed Sampling ADCs |
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