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參數(shù)資料
| 型號： | SP9380C-18 |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 50 us SETTLING TIME, 18-BIT DAC, MDIP32 |
| 封裝： | TRIPLE WIDTH, METAL, DIP-32 |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 783K |
| 代理商： | SP9380C-18 |
SPECIFICATIO N S
(Typical @25C and rated supplies.)
M ODEL
SP9380-18
SP9380-16
RESOLUTION
18-Bits
DIGITA L INPUTS
Unipolar Coding
Binary
Bipolar Coding
Offset Binary
Logic
TTL CM OS
Compatibility1
Input Leakage Current2
±1.0A
Data Setup3
150 nsec
Latch W idth
170 nsec
Data Hold4
100 nsec
A CCURA CY
Differential Nonlinearity
±0.0002% FSR typ.
±0.0008% FSR typ.
±0.0004% FSR max.
±0.0016% FSR max.
Integral Nonlinearity5
±0.0002% FSR typ,
±0.0010% FSR typ.
±0.0004% FSR max,
±0.0016% FSR max.
M onotonicity
18-Bits
16-Bits
INITIA L ERRORS
Gain
±0.01% typ. ±0.10% max
Offset
Unipolar
±0.01% typ. ±0.05% max
Bipolar
±0.01% typ. ±0.05% max
STA BILITY (ppm/ C)
Differential Nonlinearity
±0.1 typ. 0.4 max
Integral Nonlinearity
±0.2 typ. ±0.4 max
Gain
±3 typ. ±7 max
Offset
Unipolar
±0.1 typ. ±0.5 max
Bipolar
±1 typ. ±4 max
STA BILITY LONG TERM
Differential Linearity
16ppm/168hrs. @125C
1ppm/I000hrs. @25C
Gain
15ppm/I000hrs. @25C
Offset
15ppm/I000hrs. @25C
W A RM -UP TIM E
10 minutes
DY NA M IC PERFORM A NCE
A nalog Settling Time (1/2 LSB)
10 V olt Step
30sec
20 V olt Step
50sec
LSB Change
8sec
Slew Rate
2V /sec
M ajor Carry Transition Settling
to 0.006% FSR Strobed
10S
REFERENCE
V oltage
+10V (internal)
Drift
5ppm/C
Stability
1 mV /year
A NA LOG OUTPUT
V oltage
+5V , +10V , ±5V , ±10V
Noise (W ideband)
0.0004% FSR p-p
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