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參數(shù)資料
| 型號(hào)： | SP9500AS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 7.5 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 157K |
| 代理商： | SP9500AS |
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
2
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
DD - DGND .................................................................. -0.3V,+6.0V
V
REF ................................................................................ DGND, VDD
AGND .......................................................................... DGND, V
REF
D
IN .................................................................................. DGND, VDD
Power Dissipation
Plastic DIP .......................................................................... 375mW
(derate 7mW/
°C above +70°C)
Small Outline ...................................................................... 375mW
(derate 7mW/C above +70C)
SPECIFICATIONS
(Typical at 25C; T
MIN ≤ TA ≤ TMAX; VDD = +5V, DGND = 0V, VREF = +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DIGITAL INPUTS
Logic Levels
V
IH
2.4
Volts
V
IL
0.8
Volts
2 Quad, Input Coding
Binary
REFERENCE INPUTS
Note 5
V
REF Voltage Range
0.5
4.5
Volts
AGND Voltage Range
0.5
4.5
Volts
Input Resistance
11
13.9
k
D
IN = 1365; code dependent
ANALOG OUTPUT
Gain
–B, –K
±0.5
±2.0
LSB
Note 3
–A, –J
±1.0
±4.0
LSB
Note 3
±1.0
±5.0
LSB
V
REF = 4.5V; AGND = 0.5V
Initial Offset Bipolar
±0.25
±3.0
LSB
D
IN = 0
Voltage Range
0.5
4.5
Volts
Output Current
±1.0
mA
STATIC PERFORMANCE
Resolution
12
Bits
Integral Linearity
–B, –K
±0.25
±0.5
LSB
Note 3
–A, –J
±0.5
±1.0
LSB
Note 3
±0.5
LSB
V
REF = 4.5V; AGND = 0.5V
Differential Linearity
–B, –K
±0.25
±0.75
LSB
–A, –J
±0.25
±1.0
LSB
Monotonicity
Guaranteed
DYNAMIC PERFORMANCE
Settling Time
Small Signal
1
s
to 0.012%
Full Scale
7.5
s
to 0.012%, V
OUT = 0.5 to 4.5V
Slew Rate
0.6
V/
s
Multiplying Bandwidth
1.4
MHz
STABILITY
Gain
15
ppm/C
t
MIN to tMAX
Scale Zero
15
ppm/C
t
MIN to tMAX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP9500BN | SERIAL INPUT LOADING, 7.5 us SETTLING TIME, 12-BIT DAC, PDIP8 |
| SP9500BS | SERIAL INPUT LOADING, 7.5 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| SP9500AN | SERIAL INPUT LOADING, 7.5 us SETTLING TIME, 12-BIT DAC, PDIP8 |
| SP9501AN | SERIAL INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDIP8 |
| SP9501BS | SERIAL INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP9500BN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
| SP9500BS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
| SP9500JN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
| SP9500JS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
| SP9500KN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
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