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參數(shù)資料
| 型號： | SP9501AS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 159K |
| 代理商： | SP9501AS |
SP9501DS/02
SP9501 12-Bit, Low-Power Voltage Output
Copyright 2000 Sipex Corporation
5
VOUT
VREF
DAC
16
7
9
3 TO 7
DECODE
3
9
LATCH
12
1
SHIFT
REGISTER
DIN
–
+
Figure 1. Detailed Block Diagram
The operational amplifier is a rail-to-rail input,
rail-to-rail output CMOS amplifier. It is capable
of supplying 5mA of load current in the
±3 volt
output range. The initial offset voltage is laser-
trimmed to improve accuracy. Settling time is
4
s for a full scale output transition to 0.012%
accuracy.
The bipolar voltage output of the SP9501 is
created on chip from the DAC output voltage
(V
DAC) by using an operational amplifier and
two feedback resistors connected as shown in
Figure 2. This configuration produces a
±4.5V
bipolar output range with standard offset binary
coding, Table 1.
USING THE SP9501
External Reference
The DAC input resistance is code dependent
and is minimum at code 1877 and nearly infinite
at code 0. Because of the code-dependent nature
of the reference a high quality, low output im-
pedance amplifier should be used to drive
the V
REF input.
Serial Clock and Update Rate
The SP9501 maximum serial clock rate (SCLK)
is given by 1/(t
CH+tCL) which is approximately
12.5 MHz. The digital word update rate is lim-
ited by the chip select period, which is 12 X
SCLK periods plus the CS high pulse width t
CSW.
This is equal to a 1
s or 1 MHz update rate.
However, the DAC settling time to 12–Bits is 4
s, which for full scale output transitions would
limit the update rate to 250 kHz.
Logic Interface
The SP9501 is designed to be compatible with
TTL and CMOS logic levels. However, driving
the digital inputs with TTL level signals will
increase the power consumption of the part by
300
A. In order to achieve the lowest power
consumption use rail-to-rail CMOS levels to
drive the digital inputs.
Midscale Preset
By holding CS pin low during Power-up, the
DAC output can be forced to 0V. Following
Power-up, the CS pin should be kept low as the
first digital word is shifted into the shift register.
When CS pin is set high, the digital word in the
shift register (loaded by the last 12 clock cycles)
is latched into the DAC register. Thus, the DAC
can be forced to go from midscale (1000 0000
0000, on Power-up) to any digital state, without
entering an unknown state.
–
+
DIN
VREF
VOUT
VDAC
VOUT
VDAC
DIN
x VREF
DIN
WHERE
=
2048
4096
x VREF
– 1
()
Figure 2. Transfer Function
DAC
REGISTER
40K
40K
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