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參數(shù)資料
| 型號： | SP9601JS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 20 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 160K |
| 代理商： | SP9601JS |
SP9601DS/02
SP9601 12-Bit, Low-Power Voltage Output
Copyright 2000 Sipex Corporation
3
SPECIFICATIONS (continued)
(Typical at 25C; T
MIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
POWER REQUIREMENTS
Note 5
V
DD
+5V,
±3%; Note 4, 5
-J, -K
0.2
0.3
mA
-A, -B
0.2
0.45
mA
V
SS
-5V,
±3%; Note 4, 5
-J, -K
0.2
0.3
mA
-A, -B
0.2
0.45
mA
Power Dissipation
2
mW
SWITCHING
CHARACTERISTICS
CS Setup Time
(t
CSS)25
ns
SCLK Fall to CS
Fall Hold Time
(t
CSH0)20
ns
SCLK Fall to CS Rise
Hold Time
(t
CSH1)0
ns
SCLK High Width
(t
CH)40
ns
SCLK Low Width
(t
CL)40
ns
DIN Setup Time
(t
DS)50
ns
DIN Hold Time
(t
DH)0
ns
CS High Pulse Width
(t
CSW)30
ns
ENVIRONMENTAL AND
MECHANICAL
Operating Temperature
-J, -K
0
+70
°C
-A, -B
-40
+85
°C
Storage
-60
+150
°C
Package
–_N
8-pin Plastic DIP
–_S
8-pin 0.15" SOIC
Notes:
1.
Integral Linearity, for the SP9601, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
2.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
3.
1 LSB = 2*V
REF/4,096.
4.
V
REF = 0V.
5.
The following power up sequence is recommended: VSS (-5V), Vdd (+5V), VREF.
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