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參數(shù)資料
| 型號(hào)： | SPAKMC331MFC20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | User’s Manual |
| 中文描述： | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 200/254頁(yè) |
| 文件大?。?/td> | 1354K |
| 代理商： | SPAKMC331MFC20 |
MOTOROLA
A-24
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
A
Notes:
1 All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
2. In formula, n = External SCK rise + External SCK fall time
3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external sources
are at valid V
OH
/V
OL
prior to SCK transitioning between valid V
OL
and V
OH
. Due to process variation, logic decision
point voltages of the data and clock signals can differ, which can corrupt data if slower transition times are used.
Table A-9 QSPI Timing
(V
DD
= 5.0 V
dc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, 200 pF load on all QSPI pins)
Num
Function
Symbol
f
op
Min
Max
Unit
Operating Frequency
Master
Slave
Cycle Time
Master
Slave
Enable Lead Time
Master
Slave
Enable Lag Time
Master
Slave
Clock (SCK) High or Low Time
Master
Slave
2
Sequential Transfer Delay
Master
Slave (Does Not Require Deselect)
Data Setup Time (Inputs)
Master
Slave
Data Hold Time (Inputs)
Master
Slave
Slave Access Time
Slave MISO Disable Time
Data Valid (after SCK Edge)
Master
Slave
Data Hold Time (Outputs)
Master
Slave
Rise Time
Input
3
Output
Fall Time
Input
3
Output
DC
DC
1/4
1/4
System Clock Frequency
System Clock Frequency
1
t
qcyc
4
4
510
—
t
cyc
t
cyc
2
t
lead
2
2
128
—
t
cyc
t
cyc
3
t
lag
—
2
1/2
—
SCK
t
cyc
4
t
sw
2 t
cyc
– 60
2 t
cyc
– n
255 t
cyc
—
ns
ns
5
t
td
17
13
8192
—
t
cyc
t
cyc
6
t
su
30
20
—
—
ns
ns
7
t
hi
0
20
—
—
—
—
1
2
ns
ns
t
cyc
t
cyc
8
9
10
t
a
t
dis
t
v
—
—
50
50
ns
ns
11
t
ho
0
0
—
—
ns
ns
12
t
ri
t
ro
—
—
2
30
μ
s
ns
13
t
fi
t
fo
—
—
2
30
μ
s
ns
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