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參數資料
| 型號： | SPC5514GBMLQ66 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 28/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU POWERPC AN15 FIXED 144-LQFP |
| 標準包裝： | 60 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z1 |
| 芯體尺寸： | 32-位 |
| 速度： | 66MHz |
| 連通性： | CAN，EBI/EMI，I²C，SCI，SPI |
| 外圍設備： | DMA，POR，PWM，WDT |
| 輸入/輸出數： | 111 |
| 程序存儲器容量： | 512KB（512K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 數據轉換器： | A/D 40x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
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MPC5510 Microcontroller Family Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
34
2.10
eQADC Electrical Characteristics
Table 15. eQADC Conversion Specifications (Operating)
Num
Characteristic
Symbol
Min
Max
Unit
1
ADC Clock (ADCLK) Frequency1
1 Conversion characteristics vary with F
ADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a
maximum 16 factor.
FADCLK
112
MHz
2
Conversion Cycles
CC
14+2 (or 16)
14+128 (or 142)
ADCLK
cycles
3
Stop Mode Recovery Time2
2 The specified value is for the case when the 100nF capacitor is not connected to the REFBYPC pin. When the capacitor is
connected to the REFBPYC pin, the recovery time is 10ms.
TSR
20
—
μs
4
Resolution
—
1.25
—
mV
5
INL: 12 MHz ADC Clock3
3 At V
RH – VRL = 5.12 V, one lsb = 1.25 mV = one count.
INL12
—
10
Counts
6
DNL: 12 MHz ADC Clock3
DNL12
—
10
Counts
7
Offset Error with Calibration3
OFFWC
—
10
Counts
8
Full Scale Gain Error with Calibration
GAINWC
—
10
Counts
9
Disruptive Input Injection Current 4, 5, 6, 7
4 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than
VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
5 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do
not affect device reliability or cause permanent damage.
6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.
7 Condition applies to two adjacent pads on the internal pad.
IINJ
—±1
mA
10
Incremental Error due to injection current. All channels have
same 10k
Ω < Rs <100kΩ 8
Channel under test has Rs=10k
Ω,
IINJ=IINJMAX,IINJMIN
8 At V
RH – VRL = 5.12 V, one lsb = 1.25 mV = one count. This count error is in addition to the TUE count error.
EINJ
—
±6
Counts
11
Total Unadjusted Error for single ended conversions with
calibration3, 9, 10, 11, 12
9 The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
10 TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref)
11 Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification) may affect the
actual TUE measured on analog channels shared digital pins.
12 It is possible to see up to one additional count added for the 144 pin packages since the VRL and VRH functions are shared
with the VSSA and VDDA, respectively. On Analog pins above PA15, the accuracy effects from adjacent digital port pin activity
is application dependent because of frequency, level, noise, etc.
TUE
—
±10
Counts
12
Source Impedance13
13 If R
S is greater than 1 k Ohm, be sure to calculate the affect of pin leakage and use the proper sampling time, to ensure that
you get the accuracy required.
RS
—
100k
Ohm
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