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參數(shù)資料
| 型號： | SPCA514A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MOSFET; Transistor Polarity:N Channel; Drain Source Voltage, Vds:60V; Continuous Drain Current, Id:75A; On-Resistance, Rds(on):0.008ohm; Rds(on) Test Voltage, Vgs:10V; Package/Case:TO-263; Leaded Process Compatible:No RoHS Compliant: No |
| 中文描述： | 數(shù)字音頻USB控制器 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 111K |
| 代理商： | SPCA514A |
SPCA514A
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2.
The flash memory data access must be through by the CPU because the flash memory
data bus is directly connected with the CPU data bus. Therefore there are two type
pseudo DMA operations to access flash memory data to post buffer:
(1) The CPU reads the data register of the post buffer (0X8300) and the hardware
generates a write pulse to flash memory in the same time. The data flow is from post
buffer to flash memory.
(2) The CPU reads the data register of the post buffer and the hardware generates a read
pulse to flash memory in the same time. The data flow is from flash memory to post
buffer.
3. The CPU accesses flash memory data via the register (0X8400) in the direct mode.
The ECC is not generated by hardware in this mode. Therefore all accesses for the flash
memory that do not want to disturb the ECC calculation must be in this mode, for example
the additional data access.
3.5. Post buffer
3.5.1. Buffer Control
There are two 1k-byte deep FIFOs in the device to concurrently handle both incoming
and outgoing data stream in various operation modes and to easily handle data for the
USB host controller. Some detailed information about the FIFO is shown as follows.
OprMode Source
Idle
Upload 1
CPU (0X8300) Flash memory The page size of
Destination
None
FIFO Size
Note
Idle mode
FIFO mode
None
flash memory
Upload 2
Flash Memory CPU (0X8300) The page size of
flash memory
The page size of
flash memory
64 bytes
FIFO mode
Upload 3
Flash Memory USB
Pseudo DMA (2)
Upload 4
CPU (0X8300) USB
Upload 5
USB
Bulk IN pipe
Bulk OUT pipe
CPU (0X8300) 64 bytes
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