參數(shù)資料
型號(hào)： SPHE8200A
廠商： Electronic Theatre Controls, Inc.
英文描述： DVD SINGLE CHIP MPEG A/V PROCESSOR
中文描述： 影碟的單芯片MPEG A / V處理器
文件頁(yè)數(shù)： 2/40頁(yè)
文件大小： 1816K
代理商： SPHE8200A
Sun usConidenia
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5.20.
V
IDEO
DAC ....................................................................................................................................................................................23
5.21.
ATAPI
INTERFACE
...........................................................................................................................................................................23
5.22.
GPIO.............................................................................................................................................................................................23
5.23.
UART ............................................................................................................................................................................................23
6.
ELECTRICAL SPECIFICATIONS .........................................................................................................................................................24
6.1.
A
BSOLUTE
M
AXIMUM
R
ATINGS
.........................................................................................................................................................24
6.2.
DC O
PERATING
C
ONDITIONS
............................................................................................................................................................24
6.3.
C
APACITANCE
..................................................................................................................................................................................24
6.4.
AC C
HARACTERISTICS
.....................................................................................................................................................................25
6.4.1.
SDRAM interface timing diagrams ......................................................................................................................................25
6.4.2.
ROM / flash interface timing diagrams.................................................................................................................................26
6.4.3.
Audio interface timing diagrams..........................................................................................................................................27
6.4.4.
Video timing diagrams.........................................................................................................................................................28
7.
REGISTER LIST...................................................................................................................................................................................30
8.
PACKAGE/PAD LOCATION .................................................................................................................................................................38
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SPHE8200A
Table of Contents
PAGE
1.
GENERAL DESCRIPTION......................................................................................................................................................................4
2.
FEATURE ...............................................................................................................................................................................................5
3.
BLOCK DIAGRAM..................................................................................................................................................................................6
4.
SIGNAL DESCRIPTION..........................................................................................................................................................................7
4.1.
P
IN
M
AP
...........................................................................................................................................................................................7
4.2.
ROUP
M
AP
.....................................................................................................................................................................................8
4.3.
P
IN
D
ESCRIPTION
..............................................................................................................................................................................9
5.
FUNCTIONAL DESCRIPTIONS............................................................................................................................................................18
5.1.
PLL
AND
LOCK
EN
.......................................................................................................................................................................18
5.2.
P
OWER
ONTROL
...........................................................................................................................................................................18
5.3.
MBEDDED
32-
BIT
RISC C
ONTROLLER
.............................................................................................................................................18
5.4.
RISC
INTERFACE
............................................................................................................................................................................19
5.5.
ROM/F
LASH
/SRAM
CONTROLLER
....................................................................................................................................................20
5.6.
RISC M
EMORY
I
NTERFACE
..............................................................................................................................................................20
5.7.
P
ERIPHERAL
C
ONTROL
I
NTERFACE
...................................................................................................................................................20
5.8.
CSS/CPPM
SUPPORT
.....................................................................................................................................................................20
5.9.
MPEG V
IDEO
D
ECODER
..................................................................................................................................................................20
5.10.
G
RAPHICS
E
NGINE
B
ONDY
P
RO
......................................................................................................................................................21
5.11.
V
IDEO
P
OST
P
ROCESSING
...............................................................................................................................................................21
5.12.
A
UDIO
DSP ....................................................................................................................................................................................21
5.13.
A
UDIO
I
NTERFACE
...........................................................................................................................................................................22
5.14.
I
NTEGRATED
A
UDIO
Q
UALITY
ADC....................................................................................................................................................22
5.15.
I/O P
ROCESSOR
..............................................................................................................................................................................22
5.16.
SDRAM C
ONTROLLER
....................................................................................................................................................................22
5.17.
S
UB
-
PICTURE
D
ECODER
..................................................................................................................................................................22
5.18.
O
N
S
CREEN
D
ISPLAY
.......................................................................................................................................................................22
5.19.
D
ISPLAY
I
NTERFACE
.........................................................................................................................................................................22
Sunplus Technology Co., Ltd.
Proprietary & Confidential
2
OCT. 07, 2003
Preliminary Version: 0.2
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