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參數(shù)資料
| 型號： | SPL09A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5KB LCD CONTROLLER/DRIVER |
| 中文描述： | 5KB的LCD控制器/驅(qū)動 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大小： | 55K |
| 代理商： | SPL09A |
Sunplus Technology Co., Ltd. 3 Rev.: 0.1 1999.11.24
SPL09A
Preliminary
After the chip is awakened from Halt/standby State, CPU will continue to execute the next instruction. The RAM
and I/O will not be affected by wake-up.
MAP OF MEMORY AND I/Os
* I/O PORT:
H/W Register
I/Os, LCD RAM
UNUSED
USER RAM and Stack
UNUSED
SUNPLUS TEST
UNUSED
USER PROGRAM
- PORT IOCD $0004
IOEF $0005
- I/O CONFIG $0000
$0035
$0006
* NMI SOURCE
- INT1 (from TIMER 0)
* INT SOURCE
- INT0 (from TIMER 0)
- 2KHz
- T16Hz (4Hz/8Hz/16Hz/32Hz)
- 128Hz
- EXT INT (from IOCD0 pin)
- T2 Hz (2Hz/1Hz)
$0000
$0060
$00A0
$0100
$0400
$0800
$0C00
$1FFF
*MEMORY MAP (From ROM view)
TIME-SETTING REGISTER RELATED
Writing to TIME-SETTING register can program the time source of CPU wake-up and interrupt. For example,
the programmer can change 2Hz wake-up and interrupt into 1Hz wake-up and interrupt by writing 80H into $0A.
Thus, the system will wake
up to service every second. Also, T16Hz (one of counter
‘
s clock source and wake-
up & interrupt) can be one of 4Hz, 8Hz, 16Hz or 32Hz by setting bit0 and bit1 of TIME-SETTING register ($0A).
At power on state, the default value of T16Hz is 4Hz and T2Hz is 2Hz.
WATCHDOG TIMER (WDT)
An on chip watchdog timer is available on SPL09A. The WDT is designed for recovering from system abnormal
operation. If the system is hanged, WDT will generate a system reset to restart system after 1 second. If WDT
is enabled, the WDT should be cleared every 0.5 seconds to avoid accidental reset. Writing the specified value
0FH to port $0F can clear the WDT. Note that the WDT only works when 32768 Hz clock is available.
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