參數(shù)資料
型號: SPL505YC264BT
廠商: Silicon Laboratories Inc
文件頁數(shù): 9/27頁
文件大?。?/td> 0K
描述: IC CLOCK CK505 BEARLAKE 64TSSOP
標(biāo)準(zhǔn)包裝: 28
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU,PCI Express(PCIe)
輸入: 晶體
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:22
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SPL505YC26
....................Document #: 001-03543 Rev *E Page 17 of 27
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used to synchro-
nously stop and start the PCI outputs while the rest of the clock
generator continues to function. The set-up time for capturing
PCI_STP# going LOW is 10 ns (tSU). (See Figure 5.) The PCIF
clocks will not be affected by this pin if their corresponding
control bit in the SMBus register is set to allow them to be free
running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level.
DOT96C
DOT96T
CPUC(Free Running)
CPUT(Free Running)
CPUC(Stoppable)
CPUT(Stoppable)
PD#
1.8mS
CPU_STOP#
CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
Tsu
PC I_STP#
PC I_F
PC I
S R C 1 00M H z
Figure 5. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F
PCI
SRC 100MHz
Tsu
Tdrive_SRC
Figure 6. PCI_STP# Deassertion Waveform
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