MOTOROLA
INITIALIZATION AND PROGRAMMING EXAMPLES
M68HC16 Z SERIES
E-4
USER’S MANUAL
TR7
EQU $FD2E
;SPI TXD.RAM 7
TR8
EQU $FD30
;SPI TXD.RAM 8
TR9
EQU $FD32
;SPI TXD.RAM 9
TRA
EQU $FD34
;SPI TXD.RAM A
TRB
EQU $FD36
;SPI TXD.RAM B
TRC
EQU $FD38
;SPI TXD.RAM C
TRD
EQU $FD3A
;SPI TXD.RAM D
TRE
EQU $FD3C
;SPI TXD.RAM E
TRF
EQU $FD3E
;SPI TXD.RAM F
CR0
EQU $FD40
;SPI CMD.RAM 0
CR1
EQU $FD41
;SPI CMD.RAM 1
CR2
EQU $FD42
;SPI CMD.RAM 2
CR3
EQU $FD43
;SPI CMD.RAM 3
CR4
EQU $FD44
;SPI CMD.RAM 4
CR5
EQU $FD45
;SPI CMD.RAM 5
CR6
EQU $FD46
;SPI CMD.RAM 6
CR7
EQU $FD47
;SPI CMD.RAM 7
CR8
EQU $FD48
;SPI CMD.RAM 8
CR9
EQU $FD49
;SPI CMD.RAM 9
CRA
EQU $FD4A
;SPI CMD.RAM A
CRB
EQU $FD4B
;SPI CMD.RAM B
CRC
EQU $FD4C
;SPI CMD.RAM C
CRD
EQU $FD4D
;SPI CMD.RAM D
CRE
EQU $FD4E
;SPI CMD.RAM E
CRF
EQU $FD4F
;SPI CMD.RAM F
***** MCCI MODULE REGISTERS *****
MMCR
EQU $FC00
;MCCI MODULE CONFIGURATION REGISTER
MTEST
EQU $FC02
;MCCI TEST REGISTER
ILSCI
EQU $FC04
;SCI INTERRUPT LEVEL REGISTER
MIVR
EQU $FC05
;MCCI INTERRUPT VECTOR REGISTER
ILSPI
EQU $FC06
;SPI INTERRUPT LEVEL REGISTER
MPAR
EQU $FC09
;MCCI PIN ASSIGNMENT REGISTER
MDDR
EQU $FC0B
;MCCI DATA DIRECTION REGISTER
PORTMC
EQU $FC0D
;MCCI PORT DATA REGISTER
PORTMCP EQU $FC0F
;MCCI PORT PIN STATE REGISTER
SCCR0A
EQU $FC18
;SCIA CONTROL REGISTER 0
SCCR1A
EQU $FC1A
;SCIA CONTROL REGISTER 1
SCSRA
EQU $FC1C
;SCIA STATUS REGISTER
SCDRA
EQU $FC1E
;SCIA DATA REGISTER
SCCR0B
EQU $FC28
;SCIB CONTROL REGISTER 0
SCCR1B
EQU $FC2A
;SCIB CONTROL REGISTER 1
SCSRB
EQU $FC2C
;SCIB STATUS REGISTER
SCDRB
EQU $FC2E
;SCIB DATA REGISTER
SPCR
EQU $FC38
;SPI CONTROL REGISTER
SPSR
EQU $FC3C
;SPI STATUS REGISTER
SPDR
EQU $FC3E
;SPI DATA REGISTER
***** GPT MODULE REGISTERS *****
GPTMCR
EQU $F900
;GPT MODULE CONFIGURATION REGISTER
GPTMTR
EQU $F902
;GPT MODULE TEST REGISTER (RESERVED)
ICR
EQU $F904
;GPT INTERRUPT CONFIGURATION REGISTER
PDDR
EQU $F906
;PARALLEL DATA DIRECTION REGISTER
GPTPDR
EQU $F907
;PARALLEL DATA REGISTER
OC1M
EQU $F908
;OC1 ACTION MASK REGISTER
OC1D
EQU $F909
;OC1 ACTION DATA REGISTER
TCNT
EQU $F90A
;TIMER COUNTER REGISTER