參數(shù)資料
型號: SPT7824BMJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28
封裝: SIDE BRAZED, CERAMIC, DIP-28
文件頁數(shù): 6/11頁
文件大?。?/td> 112K
代理商: SPT7824BMJ
4
3/11/97
SPT7824
CLK
Output
Data
td
tpwH
N
N+1
N+2
Data Valid
N+1
Data Valid
N
N-2
N-1
tpwL
td
Data Valid
CLK
Output
Data
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
Figure 1A - Timing Diagram
Figure 1B - Single Event Clock
Table I - Timing Parameters
PARAMETERS
DESCRIPTION
MIN
TYP
MAX
UNITS
td
CLK to Data Valid Prop Delay
-
14
18
ns
tpwH
CLK High Pulse Width
10
-
300
ns
tpwL
CLK Low Pulse Width
10
-
ns
相關(guān)PDF資料
PDF描述
SPT7835SCS 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28
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