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參數(shù)資料
| 型號： | SPT7855SCU |
| 廠商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 92K |
| 代理商： | SPT7855SCU |
SPT
6
4/9/01
SPT7855
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical in-
terface requirements when using the SPT7855 in normal
circuit operation. The following sections provide descrip-
tions of the major functions and outline critical perfor-
mance criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
SPT suggests that both the digital and the analog supply
voltages on the SPT7855 be derived from a single analog
supply as shown in figure 2. A separate digital supply
should be used for all interface circuitry. SPT suggests
using this power supply configuration to prevent a possible
latch-up condition on powerup.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in
the block diagram. The design contains 16 identical suc-
cessive approximation ADC sections, all operating in par-
allel, a 16-phase clock generator, an 11-bit 16:1 digital
output multiplexer, correction logic, and a voltage refer-
ence generator that provides common reference levels for
each ADC section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
shown in table II.
VRHF
VRLS
VRLF
VRHS
VIN
CLK
VCAL
DAV
D10
D1
EN
AVDD AGND DGND* DVDD
Ref In
(+4 V)
VIN
CLK IN
Enable/Tri-State
(Enable = Active Low)
Interfacing
Logics
SPT7855
DGND
+
10 F
+5 V
Digital
+5 V
Digital
RTN
3.3/5
L1
NOTES: 1) L1 is to be located as closely to the device as possible.
2) All capacitors are 0.1 F surface-mount unless otherwise specified.
3) L1 is a 10 H inductor or a ferrite bead.
+A5
AGND
+
10 F
+5 V
Analog
+5 V
Analog
RTN
+A5
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
3.3/5
D9
D8
D7
D6
D5
D4
D3
D2
D0
DVDD
DGND
Figure 2 – Typical Interface Circuit
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參數(shù)描述 |
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| SPT7855SIS | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| SPT7855SIS_Q | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| SPT7855SIT | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| SPT7855SIT_Q | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| SPT7860 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:10-BIT, 40 MSPS, 175 mW A/D CONVERTER |
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