參數(shù)資料
型號: SPT7860SCS
元件分類: ADC
英文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28
封裝: SOIC-28
文件頁數(shù): 2/12頁
文件大?。?/td> 193K
代理商: SPT7860SCS
10
5/25/01
SPT7860
DIGITAL OUTPUTS
The digital outputs (D0–D10) are driven by a separate
supply (OVDD) ranging from +3 V to +5 V. This feature
makes it possible to drive the SPT7860’s TTL/CMOS-
compatible outputs with the user’s logic system supply.
The format of the output data (D0–D9) is straight binary.
(See table III.) The outputs are latched on the rising edge
of CLK. These outputs can be switched into a tri-state
mode by bringing EN high.
Table III – Output Data Information
ANALOG INPUT
OVERRANGE
OUTPUT CODE
D10
D9–D0
+F.S. + 1/2 LSB
1
1 1 1 1 1 1 1 1 1 1
+F.S. –1/2 LSB
0
1 1 1 1 1 1 1 1 1
+1/2 F.S.
0
+1/2 LSB
0
0 0 0 0 0 0 0 0 0
0.0 V
0
0 0 0 0 0 0 0 0 0 0
( indicates the flickering bit between logic 0 and 1.)
OVERRANGE OUTPUT
The OVERRANGE OUTPUT (D10) is an indication that
the analog input signal has exceeded the positive full-
scale input voltage by 1 LSB. When this condition occurs,
D10 will switch to logic 1. All other data outputs (D0 to D9)
will remain at logic 1 as long as D10 remains at logic 1.
This feature makes it possible to include the SPT7860 in
higher resolution systems.
EVALUATION BOARD
The EB7860 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7860.
This board includes a reference circuit, clock driver circuit,
output data latches, and an on-board reconstruction of the
digital data. An application note describing the operation
of this board, as well as information on the testing of the
SPT7860, is also available. Contact the factory for price
and availability.
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