參數(shù)資料
型號: SPT7862SIT
廠商: SIGNAL PROCESSING TECHNOLOGIES
元件分類: ADC
英文描述: DUAL 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP64
封裝: TQFP-64
文件頁數(shù): 1/10頁
文件大?。?/td> 101K
代理商: SPT7862SIT
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300
FAX: (719) 528-2370
Website: http://www.spt.com
E-Mail: sales@spt.com
SPT7862
10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER
FEATURES
Dual-channel, 10-Bit, 40 MSPS analog-to-digital
converter
Low power dissipation: 320 mW (typical)
Internal track-and-hold
Single +5 volt supply
Tri-state, TTL/CMOS-compatible outputs
Selectable +3 or +5 V logic I/O
High ESD protection of 3,500 volts minimum
APPLICATIONS
Video set-top boxes
Cellular base stations
QPSK/QAM RF demodulation
S-video digitizers
Composite video digitizers
Portable and handheld instrumentation
Medical ultrasound
Cable modems
Video frame grabbers
GENERAL DESCRIPTION
The SPT7862 contains two separate 10-bit CMOS analog-
to-digital converters that have sampling rates of up to 40
MSPS. Each device has its own separate clock and refer-
ence inputs so that they can be used independently in
multichannel applications or can be driven from the same
inputs for demanding quadrature demodulation and S-video
applications. On-chip track-and-hold and advanced propri-
etary circuit design in a CMOS process technology provide
very good dynamic performance.
The SPT7862 operates from a single +5 V supply. Digital
data outputs are user selectable at +3 or +5 V. Output data
format is straight binary.
The SPT7862 is available in a 64-lead TQFP package
(10 x 10 mm) over the industrial temperature range of
–40
°C to +85 °C.
ADC
Reference
Ladder
Timing
Generation
VINA
VRHFA
VRHSA
VRLFA
VRLSA
CLK A
ADC
Reference
Ladder
Timing
Generation
VINB
VRHFB
VRHSB
VRLFB
VRLSB
CLK B
Output
Buffers
OVDDA (+3.3/5.0 V)
DA9–0
EN
Output
Buffers
OVDDB (+3.3/5.0 V)
DB9–0
AVDD
AGND
DVDD
DGND
VINRA
VINRB
OGNDA
OGNDB
DAVB
DAVA
BLOCK DIAGRAM
相關(guān)PDF資料
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