SRM-155 SONET/SDH Receiver Module
Product Data Sheet
VI
603-598-0070
3
Figure 2. Pin Diagram (Top View)
Table 1. Pin Function
Pin
Symbol
Function
4
Clock
PECL Recovered Clock Output.
5
Clock
PECL Complementary Recovered Clock Output.
7
Data
PECL Retimed Data Output.
9
Data
PECL Complementary Retimed Data Output.
10
V
D
Detector Anode Bias. Ground or apply +5 Volt bias through a series resistor for
received optical power monitoring.
1
11
V
CC
5 Volt Supply Voltage.
12
Flag
Input Signal Level Status. This CMOS output switches low when the received
optical power falls below the status minimum optical power level.
14
Flag
Complementary Input Signal Status. CMOS complement of Flag.
1,2,3,6,8,13,15,16
GND
Ground.
17,18,19,20
1. By connecting pin 10 to a +5 Volt bias through a series resistor (eg. 1 k
) received optical power can be monitored as a voltage drop across the resistor.
Absolute Maximum Ratings
Absolute maximum ratings are provided here as
worst case and short duration exposure conditions
only. Exposure to conditions more severe than the
Absolute Maximum Ratings may result in permanent
damage. Exposure to conditions at the Absolute
Table 2. Absolute Maximum Ratings
Parameter
Symbol
NC
No User Connection.
Maximum Ratings for extended periods may also
adversely affect device performance or reliability.
Functional operation of the device is not implied at
these conditions.
Minimum
Maximum
Units
Storage Temperature Range
T
S
-40
85
°C
Supply Voltage
V
CC
0
+6
V
pin Detector Bias
V
D
0
+6
V
Lead Soldering Conditions
250/10
°C/s
Pin 1 Indicator
Top View
10
11
20