參數(shù)資料
型號： SSM2604CPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 5/28頁
文件大小： 0K
描述： IC AUDIO CODEC LP 20-LFCSP
標準包裝： 1
類型： 立體聲音頻
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標準 ADC / DAC (db)： 90 / 100
電壓 - 電源，模擬： 1.8 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.5 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-VFQFN 裸露焊盤，CSP
供應商設(shè)備封裝： 20-LFCSP-VQ
包裝： 標準包裝
其它名稱： SSM2604CPZ-REEL7DKR
Data Sheet
SSM2604
Rev. A | Page 13 of 28
audio frame clock signal that separates left- and right-channel
data on the PBDAT lines.
The BCLK signal acts as the digital audio clock. Depending on
if the SSM2604 is in master or slave mode, the BCLK signal is
either an input or an output signal. During a playback opera-
tion, PBDAT and PBLRC must be synchronous to the BCLK
signal to avoid data corruption.
Digital Audio Data Sampling Rate
To accommodate a wide variety of commonly used DAC and
ADC sampling rates, the SSM2604 allows for two modes of
operation, normal and USB, selected by the USB bit (Register R8,
Bit D0).
In normal mode, the SSM2604 supports digital audio sampling
rates from 8 kHz to 96 kHz. Normal mode supports 256 fS and
384 fS based clocks. To select the desired sampling rate, the user
must set the appropriate sampling rate register in the SR control
bits (Register R8, Bit D2 to Bit D5) and match this selection to
the core clock frequency that is pulsed on the MCLK pin. See
Table 25 and Table 26 for guidelines.
In USB mode, the SSM2604 supports digital audio sampling
rates from 8 kHz to 96 kHz. USB mode is enabled on the
SSM2604 to support the common universal serial bus (USB)
clock rate of 12 MHz, or to support 24 MHz if the CLKDIV2
control register bit is activated. The user must set the appropriate
sampling rate in the SR control bits (Register R8, Bit D2 to Bit D5).
Note that the sampling rate is generated as a fixed divider from
the MCLK signal. Because all audio processing references the
core MCLK signal, corruption of this signal, in turn, corrupts
the outgoing audio quality of the SSM2604. The BCLK/RECLRC/
RECDAT or BCLK/PBLRC/PBDAT signals must be synchronized
with MCLK in the digital audio interface circuit. MCLK must
be faster or equal to the BCLK frequency to guarantee that no
data is lost during data synchronization.
The BCLK frequency should be greater than
Sampling Rate × Word Length × 2
Ensuring that the BCLK frequency is greater than this value
guarantees that all valid data bits are captured by the digital
audio interface circuitry. For example, if a 32 kHz digital
audio sampling rate with a 32-bit word length is desired,
BCLK ≥ 2.048 MHz.
RECLRC/
PBLRC
BCLK
RECDAT/
PBDAT
12
3
4
N
X
N
1
2
LEFT CHANNEL
3
RIGHT CHANNEL
1/
fS
X = DON’T CARE.
0
69
78-
0
13
Figure 19. Left-Justified Audio Input Mode
RECLRC/
PBLRC
BCLK
RECDAT/
PBDAT
LEFT CHANNEL
RIGHT CHANNEL
1/
fS
X = DON’T CARE.
XN
X
3
21X
X
N
4
43
21
06
97
8-
01
4
Figure 20. Right-Justified Audio Input Mode
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